參數(shù)資料
型號: CAT24WC256JA3TE13
元件分類: EEPROM
英文描述: 256K-Bit I2C Serial CMOS EEPROM
中文描述: 256K位I2C串行CMOS EEPROM的
文件頁數(shù): 3/10頁
文件大?。?/td> 417K
代理商: CAT24WC256JA3TE13
CAT24WC256
3
Doc. No. 1031, Rev. F
Note:
(1) AC measurement conditions:
RL (connects to V
CC
): 0.3V
CC
to 0.7 V
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
V
CC
=1.8V - 6.0V
Min
V
CC
=2.5V - 6.0V
Min
V
CC
=3.0V - 5.5V
Min
Max
Max
Max
Units
F
SCL
Clock Frequency
100
400
1000
kHz
t
AA
SCL Low to SDA Data Out
and ACK Out
0.1
3.5
0.05
0.9
0.05
0.55
μ
s
t
BUF(2)
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.2
0.5
μ
s
t
HD:STA
Start Condition Hold Time
4.0
0.6
0.25
μ
s
μ
s
μ
s
μ
s
t
LOW
Clock Low Period
4.7
1.2
0.6
t
HIGH
Clock High Period
4.0
0.6
0.4
t
SU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.0
0.6
0.25
t
HD:DAT
Data In Hold Time
0
0
0
ns
t
SU:DAT
t
R(2)
t
F(2)
Data In Setup Time
100
100
100
ns
SDA and SCL Rise Time
1.0
0.3
0.3
μ
s
SDA and SCL Fall Time
300
300
100
ns
t
SU:STO
Stop Condition Setup Time
4.7
0.6
0.25
μ
s
t
DH
Data Out Hold Time
100
50
50
ns
t
WR
Write Cycle Time
10
10
10
ms
Power-Up Timing
(2)(3)
Symbol
Parameter
Min
Typ
Max
Units
t
PUR
Power-Up to Read Operation
1
ms
t
PUW
Power-Up to Write Operation
1
ms
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