參數(shù)資料
型號: CAT24WC33JA-1.8TE13D
英文描述: 32K/64K-Bit I2C Serial CMOS EEPROM
中文描述: 32K/64K-Bit I2C串行CMOS EEPROM的
文件頁數(shù): 3/12頁
文件大?。?/td> 643K
代理商: CAT24WC33JA-1.8TE13D
DsconinuedPats
t
WR
Write Cycle Time
CAT24WC33/65
3
Doc No. 1049, Rev. D
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
A.C. CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Power-Up Timing
(1)(2)
Symbol
Parameter
Max.
Units
PUR
Power-Up to Read Operation
1
ms
PUW
Power-Up to Write Operation
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
Units
10
ms
l
b
m
y
S
F
r
q
p
A
w
m
F
k
S
S
,
C
L
L
C
S
O
m
w
N
S
k
C
k
C
S
r
A
S
A
S
p
S
r
N
S
C
8
X
V
.
M
0
0
1
X
C
W
5
V
4
2
T
8
.
M
A
C
X
X
5
.
M
C
W
4
2
T
A
V
0
1
C
U
H
k
5
V
5
.
M
V
0
4
5
V
.
0
M
.
0
M
L
C
S
y
p
S
z
T
I
)
C
m
0
0
2
0
0
2
0
0
2
A
A
K
C
A
O
A
5
5
1
μ
F
U
B
)
B
S
F
m
C
b
m
H
p
H
p
S
L
C
S
L
C
S
C
H
O
M
B
T
L
g
H
C
R
h
7
7
2
μ
A
T
S
:
H
S
S
m
m
R
l
F
S
m
w
h
C
4
4
6
2
6
μ
μ
μ
W
O
L
7
4
7
4
H
G
I
H
A
T
S
:
U
S
m
C
p
)
7
7
6
μ
R
F
S
H
T
A
:
H
0
5
0
5
0
5
μ
μ
T
A
:
U
)
S
0
0
0
m
m
p
1
0
1
0
3
0
3
)
0
3
0
3
0
O
T
S
:
U
m
4
0
4
0
6
0
1
0
1
0
1
0
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