參數(shù)資料
型號: CAT25C16YE-1.8T3
英文描述: 8K/16K SPI Serial CMOS EEPROM
中文描述: 8K/16K SPI串行EEPROM中的CMOS
文件頁數(shù): 5/16頁
文件大?。?/td> 550K
代理商: CAT25C16YE-1.8T3
5
CAT25C08/16
Doc. No. 1016, Rev. C
2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Status Register Bits
BP1
0
Array Address
Protected
None
Protection
BP0
0
No Protection
0
1
25C08: 0300-03FF
25C16: 0600-07FF
Quarter Array Protection
1
0
25C08: 0200-03FF
25C16: 0400-07FF
Half Array Protection
1
1
25C08: 0000-03FF
25C16: 0000-07FF
Full Array Protection
BLOCK PROTECTION BITS
7
6
5
4
3
2
1
0
WPEN
0
1
0
BP1
BP0
WEL
RDY
STATUS REGISTER
Protected
Blocks
Protected
Unprotected
Blocks
Protected
Status
Register
Protected
WPEN
0
WP
X
WEL
0
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
WRITE PROTECT ENABLE OPERATION
and the 25C08/16. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
CS
:
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C08/
16 and
CS
high disables the CAT25C08/16.
CS
high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway) The CAT25C08/16 draws
ZERO current in the Standby mode. A high to low
transition on
CS
is required prior to any sequence being
initiated. A low to high transition on
CS
after a valid write
sequence is what initiates an internal write cycle.
BYTE ADDRESS
Device
CAT25C08
CAT25C16
Address Significant Bits
A9 - A0
A10 - A0
Address Don't Care Bits
A15 - A10
A15 - A11
# Address Clock Pulse
16
16
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