參數(shù)資料
型號: CAT25C256U14-TE13
元件分類: EEPROM
英文描述: 64K 8K x 8 Battery-Voltage CMOS E2PROM
中文描述: 64K的8K的× 8電池電壓的CMOS E2PROM的
文件頁數(shù): 10/11頁
文件大小: 79K
代理商: CAT25C256U14-TE13
10
CAT25C128/256
Doc. No. 25088-00 1/01
Figure 9.
HOLD
Timing
DESIGN CONSIDERATIONS
The CAT25C128/256 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up
CS
should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write the
CAT25C128/256 goes into a write disable mode.
CS
must be set high after the proper number of clock cycles
to start an internal write cycle. Access to the array during
an internal write cycle is ignored and programming
is continued. On power up, SO is in a high impedance.
If an invalid op code is received, no data will be shifted
into the CAT25C128/256, and the serial output pin (SO)
will remain in a high impedance state until the falling
edge of
CS
is detected again.
CS
SCK
HOLD
SO
tCD
tHD
tHD
tCD
tLZ
tHZ
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
t
CSH
CS
SCK
WP
WP
t
WPS
t
WPH
Figure 10.
WP
Timing
Note: Dashed Line= mode (1, 1) — — — —
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