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參數(shù)資料
| 型號： | CAT25C32U20S-1.8TE13 |
| 英文描述： | 32K/64K-Bit SPI Serial CMOS EEPROM |
| 中文描述： | 32K/64K-Bit SPI串行EEPROM中的CMOS |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 82K |
| 代理商： | CAT25C32U20S-1.8TE13 |
5
CAT25C32/64
Doc. No. 1001, Rev. G
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
WEL
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
WRITE PROTECT ENABLE OPERATION
the communication between the microcontroller and the
25C32/64. Opcodes, byte addresses, or data present on
the SI pin are latched on the rising edge of the SCK. Data
on the SO pin is updated on the falling edge of the SCK.
CS
: Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C32/
64 and
CS
high disables the CAT25C32/64.
CS
high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway). The CAT25C32/64 draws
ZERO current in the Standby mode. A high to low
transition on
CS
is required prior to any sequence being
initiated. A low to high transition on
CS
after a valid write
sequence is what initiates an internal write cycle.
WP
: Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low and the WPEN bit in the status
register is set to
“
1
”
, all write operations to the status
register are inhibited.
WP
going low while
CS
is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP
going low will
have no effect on any write operation to the status
register. The
WP
pin function is blocked when the WPEN
bit is set to 0.
HOLD
: Hold
The
HOLD
pin is used to pause transmission to the
CAT25C32/64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,
HOLD
must be brought low while SCK
is low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication,
HOLD
is brought
high, while SCK is low.
(HOLD
should be held high any
time this function is not being used.)
HOLD
may be tied
high directly to V
cc
or tied to V
cc
through a resistor.
Figure 9 illustrates hold timing sequence.
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
STATUS REGISTER
Status Register Bits
BP1
Array Address
Protected
Protection
BP0
0
0
None
No Protection
0
1
25C32: 0C00-0FFF
25C64:1800-1FFF
Quarter Array Protection
1
0
25C32: 800-0FFF
25C64:1000-1FFF
Half Array Protection
1
1
25C32: 0000-0FFF
25C64:0000-1FFF
Full Array Protection
BLOCK PROTECTION BITS
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| CAT25C32U20SATE13 | 32K/64K-Bit SPI Serial CMOS EEPROM |
| CAT25C32U20SE-1.8TE13 | 32K/64K-Bit SPI Serial CMOS EEPROM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CAT25C32V | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C32V-1.8 | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 1.8-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C32V-1.8-TE13 | 制造商:ON Semiconductor 功能描述:EEPROM Serial-SPI 32K-Bit 4K x 8 2.5V/3.3V/5V 8-Pin SOIC N T/R |
| CAT25C32VA | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C32VI | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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