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參數(shù)資料
| 型號(hào)： | CAT25C33GLSI-1.8TE13 |
| 英文描述： | 32K/64K-Bit SPI Serial CMOS EEPROM |
| 中文描述： | 32K/64K-Bit SPI串行EEPROM中的CMOS |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 325K |
| 代理商： | CAT25C33GLSI-1.8TE13 |
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8
CAT25C33/65
Doc. No. 1000, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 7. WRSR Instruction Timing
Figure 6. Write Instruction Timing
Note: Dashed Line= mode (1, 1)
–
–
–
–
Note: Dashed Line= mode (1, 1)
—
—
—
—
SK
SI
SO
0
0
0
0
0
0
1
0
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
0
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
31
CS
OPCODE
DATA IN
HIGH IMPEDANCE
0
1
2
3
4
5
6
7
8
10
9
11
12
13
14
SCK
SI
MSB
HIGH IMPEDANCE
DATA IN
15
SO
CS
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
OPCODE
If the write operation is initiated immediately after the
WREN instruction without
CS
being brought high,
the data will not be written to the array because the
write enable latch will not have been properly set.
Also, for a successful write operation the address of
the memory location(s) to be programmed must be
outside the protected address field location selected
by the block protection level.
Byte Write
Once the device is in a Write Enable state, the user
may proceed with a write sequence by setting the
CS
low, issuing a write instruction via the SI line, followed
by the 16-bit address (the three Most Significant Bits
are don
’
t care for 25C65 and four most significant bits
are don't care for 25C33), and then the data to be
written. Programming will start after the
CS
is
brought high. Figure 6 illustrates byte write se-
quence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
The Status Register can be read to determine if the write cycle
is still in progress. If Bit 0 of the Status Register is set at 1, write
cycle is in progress. If Bit 0 is set at 0, the device is ready for
the next instruction.
Page Write
The CAT25C33/65 features page write capability. After the first
initial byte the host may continue to write up to 64 bytes of data
lower order address bits are internally incremented by one; the
high order bits of address will remain constant. The only
restriction is that the 64 bytes must reside on the same page.
If the address counter reaches the end of the page and clock
continues, the counter will
“
roll over
”
to the first address of the
page and overwrite any data that may have been written. The
CAT25C33/65 is automatically returned to the write disable
state at the completion of the write cycle. Figure 8 illustrates the
page write sequence.
To write to the status register, the WRSR instruction should be
sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be
written using the WRSR instruction. Figure 7 illustrates the
sequence of writing to status register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT25C33L | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33L-1.8 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 1.8-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33LA | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33LI | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33LI-1.8 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 1.8-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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