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參數(shù)資料
| 型號： | CAT25C33GLSTE13 |
| 英文描述： | 32K/64K-Bit SPI Serial CMOS EEPROM |
| 中文描述： | 32K/64K-Bit SPI串行EEPROM中的CMOS |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 325K |
| 代理商： | CAT25C33GLSTE13 |
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7
CAT25C33/65
Doc No. 1000, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 4. Read Instruction Timing
Figure 5. RDSR Instruction Timing
Note: Dashed Line= mode (1, 1)
—
—
—
—
Note: Dashed Line= mode (1, 1)
—
—
—
—
SK
SI
SO
0
0
0
0
0
0
1
1
BYTE ADDRESS*
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
0
*Please check the instruction set table for address
CS
OPCODE
DATA OUT
MSB
HIGH IMPEDANCE
0
1
2
3
4
5
6
7
8
10
9
11
12
13
14
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
CS
0
0
0
0
0
1
0
1
up in a write disable state when V
cc
is applied. WREN
instruction will enable writes (set the latch) to the device.
WRDI instruction will disable writes (reset the latch) to
the device. Disabling writes will protect the device
against inadvertent writes.
READ Sequence
The part is selected by pulling
CS
low. The 8-bit read
by the 16-bit address(the three Most Significant Bits are
don
’
t care for 25C65 and four most significant bits are
don't care for 25C33). After the correct read instruction
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address (1FFFh for 25C65
and FFFh for 25C33) is reached, the address counter rolls
over to 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by pulling the
CS
high. To read the status register, RDSR instruction
should be sent. The contents of the status register are
shifted out on the SO line. The status register may be read
at any time even during a write cycle. Read sequece is
illustrated in Figure 4. Reading status register is illustrated
in Figure 5.
WRITE Sequence
The CAT25C33/65 powers up in a Write Disable state. Prior
to any write instructions, the WREN instruction must be
sent to CAT25C33/65. The device goes into Write enable
state by pulling the
CS
low and then clocking the WREN
instruction into CAT25C33/65. The
CS
must be brought
high after the WREN instruction to enable writes to the
device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT25C33L | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33L-1.8 | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 1.8-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33LA | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33LI | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33LI-1.8 | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 1.8-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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