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參數資料
| 型號： | CAT25C33GVSETE13 |
| 英文描述： | 32K/64K-Bit SPI Serial CMOS EEPROM |
| 中文描述： | 32K/64K-Bit SPI串行EEPROM中的CMOS |
| 文件頁數： | 6/11頁 |
| 文件大?。?/td> | 325K |
| 代理商： | CAT25C33GVSETE13 |
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6
CAT25C33/65
Doc. No. 1000, Rev. H
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 2. WREN Instruction Timing
Figure 3. WRDI Instruction Timing
Note: Dashed Line= mode (1, 1)
—
—
—
—
Note: Dashed Line= mode (1, 1)
—
—
—
—
SK
SI
CS
SO
0
0
0
0
0
1
1
0
HIGH IMPEDANCE
SK
SI
CS
SO
0
0
0
0
0
1
0
0
HIGH IMPEDANCE
directly to V
cc
or tied to V
cc
through a resistor. Figure
9 illustrates hold timing sequence.
STATUS REGISTER
The Status Register indicates the status of the device.
The
RDY
(Ready) bit indicates whether the CAT25C33/
65 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a
Write Enable state and when set to 0 the device is in
a Write Disable state. The WEL bit can only be set by
the WREN instruction and can be reset by the WRDI
instruction.
The BP0, BP1 and BP2 (Block Protect) bits indicate
which blocks are currently protected. These bits are
set by the user issuing the WRSR instruction. The user
is allowed to protect any quarter of the memory, the
lower half of the memory, the first page or the last page by
setting these bits. Once protected the user may only
read from the protected portion of the array. These bits are
non-volatile.
The WPEN (Write Protect Enable) is an enable bit for the
WP
pin. The
WP
pin and WPEN bit in the status register control
the programmable hardware write protect feature.Hardware
write protection is enabled when
WP
is low and WPEN bit
is set to high. The user cannot write to the status register
(including the block protect bits and the WPEN bit) and the
block protected sections in thememory array when the chip
is hardware write protected. Only the sections of the
memory array that are not block protected can be written.
Hardware write protection is disabled when either
WP
pin is
high or the WPEN bit is zero.
DEVICE OPERATION
Write Enable and Disable
The CAT25C33/65 contains a write enable latch. This latch
must be set before any write operation. The device powers
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CAT25C33L | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33L-1.8 | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 1.8-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33LA | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33LI | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C33LI-1.8 | 功能描述:電可擦除可編程只讀存儲器 (4kx8) 32K 1.8-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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