參數(shù)資料
型號: CAT28HT256
英文描述: 256K-Bit CMOS Parallel EEPROM(5V,快速,低功耗,256K位(32K x 8位)并行CMOS EEPROM)
中文描述: 256K位CMOS并行的EEPROM(5V的,快速,低功耗,256K位(32K的× 8位)并行的CMOS EEPROM的)
文件頁數(shù): 9/10頁
文件大小: 218K
代理商: CAT28HT256
CAT28HT256
8-99
Advanced
Stock No. 21065-03 2/98
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transi-
tions. This gives the user added inadvertent write pro-
tection on power-up in addition to the hardware protec-
tion provided.
To allow the user the ability to program the device with
an E
2
PROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
5096 FHD F13
CE
WE
tWP
AA
5555
55
2AAA
A0
5555
DATA
ADDRESS
tBLC
tWC
BYTE OR
PAGE
WRITES
ENABLED
Figure 12. Resetting Software Data Protection Timing
CE
WE
AA
5555
55
2AAA
DATA
ADDRESS
tWC
80
5555
AA
5555
55
2AAA
20
5555
SDP
RESET
DEVICE
UNPROTECTED
5096 FHD F14
ORDERING INFORMATION
Notes:
(1)
The device used in the above example is a CAT28HT256HD-20 (100,000 Cycle Endurance, CERDIP, 200 ns Access Time).
28HT256 F16
Speed
20: 200ns
25: 250ns
Prefix
Device #
Suffix
28HT256
Product
Number
CAT
Optional
Company
ID
-20
Package
D: CERDIP
D
H
Endurance
Blank = 10,000 Cycle
H = 100,000 Cycle
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