參數(shù)資料
型號: CAT28LV256
英文描述: 256K-Bit CMOS Parallel EEPROM(低壓,快速,低功耗,256K位(32K x 8位)并行CMOS EEPROM)
中文描述: 256K位CMOS并行的EEPROM(低壓,快速,低功耗,256K位(32K的× 8位)并行的CMOS EEPROM的)
文件頁數(shù): 7/10頁
文件大?。?/td> 71K
代理商: CAT28LV256
CAT28LV256
7
Preliminary
Doc. No. 25040-00 2/98
OE
CE
WE
ADDRESS
I/O
tWP
tBLC
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
LAST BYTE
tWC
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN
DATA VALID
HIGH-Z
tAH
tWC
tOEH
tDH
tDS
tOES
tBLC
tCH
tCS
tCW
Page Write
The page write mode of the CAT28LV256 (essentially
an extended BYTE WRITE mode) allows from 1 to 64
bytes of data to be programmed within a single E
2
PROM
write cycle. This effectively reduces the byte-write time
by a factor of 64.
Following an initial WRITE operation (
WE
pulsed low, for
t
WP
, and then high) the page write mode can begin by
issuing sequential
WE
pulses, which load the address
and data bytes into a 64 byte temporary buffer. The page
address where data is to be written, specified by bits A
6
to A
14
, is latched on the last falling edge of
WE
. Each
byte within the page is defined by address bits A
0
to A
5
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within t
BLC MAX
of the rising edge of the
preceding
WE
pulse. There is no page write window
limitation as long as
WE
is pulsed low within t
BLC MAX
.
Upon completion of the page write sequence,
WE
must
stay high a minimum of t
BLC MAX
for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
Figure 5. Byte Write Cycle [
CE
Controlled]
28LV256 F08
Figure 6. Page Mode Write Cycle
28LV256 F09
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