參數(shù)資料
型號(hào): CAT28LV64JA-25T
元件分類(lèi): PROM
英文描述: 8K X 8 EEPROM 3V, 250 ns, PDSO28
封裝: SOIC-28
文件頁(yè)數(shù): 10/12頁(yè)
文件大小: 527K
代理商: CAT28LV64JA-25T
CAT28LV64
7
Doc. No. 1010, Rev. D
Doc. No. 1010, Rev. A
OE
CE
WE
ADDRESS
I/O
tWP
tBLC
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
LAST BYTE
tWC
Page Write
The page write mode of the CAT28LV64 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
of data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte-write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 32 byte temporary buffer. The page
address where data is to be written, specified by bits A5
to A12, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A4
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within tBLC MAX.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLCMAX for the internal automatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that
existed in each addressed cell, and a write cycle, which
writes new data back into the cell. A page write will only
write data to the locations that were addressed and will
not rewrite the entire page.
Figure 5. Byte Write Cycle [CE Controlled]
Figure 6. Page Mode Write Cycle
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN
DATA VALID
HIGH-Z
tAH
tWC
tOEH
tDH
tDS
tOES
tBLC
tCH
tCS
tCW
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