參數(shù)資料
型號(hào): CAT40C00GLETE13
元件分類: EEPROM
英文描述: 128-Bit Serial EEPROM
中文描述: 128位串行EEPROM
文件頁數(shù): 4/10頁
文件大?。?/td> 631K
代理商: CAT40C00GLETE13
DsconinuedPat
Figure 3. Start/Stop Timing
CAT24C00
4
Doc. No. 1027, Rev. O
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FUNCTIONAL DESCRIPTION
The CAT24C00 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24C00 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24C00 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input
pin.
SDA:
Serial Data/Address
The CAT24C00 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
5020 FHD F05
5020 FHD F04
5020 FHD F03
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL
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