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參數(shù)資料
| 型號： | CAT5136SDI-50GT3 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DPP I2C 128TAP VOL SC70-6 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
CAT5136, CAT5137, CAT5138
http://onsemi.com
7
DEVICE DESCRIPTION
Slave Address Instruction Byte Description
The first byte sent to the CAT513x from the master
processor is called the Slave Address Byte. The most
significant seven bits of the slave address are a device type
identifier. For CAT5136 and CAT5137 these bits are fixed
at 0101110. For CAT5138, they are 0111110. This allows
both CAT5137 and CAT5138, which are functionally
identical, to reside on the same bus (refer to Table 10).
Only the device with slave address matching the input
byte will be accessed by the master.
The last bit is the READ/WRITE bit and determines the
function to be performed. If it is a “1” a read command is
initiated and if it is a “0” a write is initiated.
After the Master sends a START condition and the slave
address byte, the CAT513x monitors the bus and responds
with an acknowledge when its address matches the
transmitted slave address.
Table 10. BYTE 1 SLAVE ADDRESS AND INSTRUCTION BYTE
Device
Device Type Identifier
Read/Write
ID6
ID5
ID4
ID3
ID2
ID1
ID0
CAT5136
0
1
0
1
0
R/W
CAT5137
0
1
0
1
0
R/W
CAT5138
0
1
0
R/W
(MSB)
(LSB)
Wiper Control Register (WCR) Description
The CAT513x contains a 7-bit volatile Wiper Control
Register which is decoded to select one of the 128 switches
along its resistor array. The Wiper Control Register loses its
contents when the CAT513x is powered-down. At
power-up, the register is loaded with the midscale value 40h.
The contents of the WCR may be read or changed directly
by the host using a READ/WRITE command on the I2C bus
(see Table 1 to access WCR). Since the CAT513x will only
make use of the 7 LSB bits, the first data bit, or MSB, is
ignored on write instructions and will always come back as
a “0” on read commands.
A write operation (see Table 11) requires a Start condition,
followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the
three bytes, the CAT513x responds with an acknowledge.
After the third byte, the data is written to the Wiper Control
Register, and the wiper changes position accordingly.
A read operation (see Table 12) requires a Start condition,
followed by a valid slave address byte for write, a valid
address byte 00h, a second START and a second slave
address byte for read. After each of the three bytes, the
CAT513x responds with an acknowledge and then the
device transmits the data byte. The master terminates the
read operation by issuing a STOP condition following the
last bit of Data byte.
Table 11. WRITE OPERATION
CAT5136 and CAT5137
ST
AR
T
1st byte
ACK
2nd byte
ACK
3rd byte
ACK
ST
OP
SLAVE
ADDRESS
Wb
ADDRESS
BYTE
DATA BYTE IN
S 0 1 0 1 1 1 0 0 A 0 0 0 0 0 0 0 0 A X D6 D5 D4 D3 D2 D1 D0 A P
CAT5138
ST
AR
T
1st byte
ACK
2nd byte
ACK
3rd byte
ACK
ST
OP
SLAVE
ADDRESS
Wb
ADDRESS
BYTE
DATA BYTE IN
S 0 1 1 1 1 1 0 0 A 0 0 0 0 0 0 0 0 A X D6 D5 D4 D3 D2 D1 D0 A P
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