參數(shù)資料
型號(hào): CAT5171TBI-50GT3
廠商: ON Semiconductor
文件頁(yè)數(shù): 11/12頁(yè)
文件大小: 0K
描述: IC POT DGTL 50K 256TAP SOT23-8
標(biāo)準(zhǔn)包裝: 3,000
接片: 256
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 100 ppm/°C
存儲(chǔ)器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 帶卷 (TR)
CAT5171
http://onsemi.com
8
ESD Protection
GND
LOGIC
Digital
Input
GND
Potentiometer
Figure 12. ESD Protection Networks
W, A, B
Terminal Voltage Operating Range
The CAT5171 VDD and GND power supply define the
limits for proper 3-terminal digital potentiometer operation.
Signals or potentials applied to terminals A, B or the wiper
must remain inside the span of VDD and GND. Signals
which attempt to go outside these boundaries will be
clamped by the internal forward biased diodes.
W, A, B
CAT5171
LOGIC
GND
Figure 13.
VDD
Power-up Sequence
Because ESD protection diodes limit the voltage
compliance at terminals A, B, and W (see Figure 12), it is
recommended that VDD/GND be powered before applying
any voltage to terminals A, B, and W. The ideal powerup
sequence is: GND, VDD, digital inputs, and then VA/B/W. The
order of powering VA, VB, VW, and the digital inputs is not
important as long as they are powered after VDD/GND.
Power Supply Bypassing
Good design practice employs compact, minimum lead
length layout design. Leads should be as direct as possible.
It is also recommended to bypass the power supplies with
quality low ESR Ceramic chip capacitors of 0.01
mF to
0.1
mF. Low ESR 1 mF to 10 mF tantalum or electrolytic
capacitors can also be applied at the supplies to suppress
transient disturbances and low frequency ripple. As a further
precaution digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
CAT5171
GND
+
10 mF
0.1 mF
Figure 14. Power Supply Bypassing
VDD
C3
C1
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