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參數(shù)資料
| 型號： | CAT5251JI-50TE13 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digitally Programmable Potentiometer (DPP) with 256 Taps and SPI Interface |
| 中文描述： | 四數(shù)字可編程電位（民進黨）與256水龍頭和SPI接口 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 95K |
| 代理商： | CAT5251JI-50TE13 |
2
CAT5251
Document No. 2017, Rev. D
being initiated. A low to high transition on
CS
after a valid write sequence is what initiates an internal write cycle.
WP
:
WP
is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When
WP
is tied low, all
non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed).
WP
going low while
CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated,
WP
going low will have no
effect on any write operation.
Write Protect
HOLD
:
The
HOLD
pin is used to pause transmission to the CAT5251 while in the middle of a serial sequence without having to re-
transmit entire sequence at a later time. To pause,
HOLD
must be brought low while SCK is low. The SO pin is in a high imped-
ance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication,
HOLD
is
brought high, while SCK is low. (
HOLD
should be held high any time this function is not being used.)
HOLD
may be tied high
directly to VCC or tied to VCC through a resistor.
Hold
PIN DESCRIPTION
Pin
(SOIC/TSSOP)
Name
Function
1
2
3
4
SO
A0
R
W3
R
H3
Serial Data Output
Device Address, LSB
Wiper Terminal for Potentiometer 3
High Reference Terminal
for Potentiometer 3
Low Reference Terminal
for Potentiometer 3
No Connect
Supply Voltage
Low Reference Terminal
for Potentiometer 0
High Reference Terminal
for Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal
for Potentiometer 1
High Reference Terminal
for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
Wiper Terminal for
Potentiometer 2
High Reference Terminal
for Potentiometer 2
Low Reference Terminal
Bus Serial Clock
5
R
L3
6
7
8
NC
VCC
R
L0
9
R
H0
10
11
12
13
14
15
R
W0
CS
WP
SI
A1
R
L1
16
R
H1
17
18
19
20
R
W1
GND
NC
R
W2
21
R
H2
22
R
L2
23
SCK
24
HOLD
Hold
PIN DESCRIPTIONS
SI:
SI is the serial data input pin. This pin is used to
input all opcodes, byte addresses and data to be
written to the CAT5251. Input data is latched on the
rising edge of the serial clock.
Serial Input
SO:
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5251. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
Serial Output
SCK:
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5251. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
Serial Clock
A0, A1: Device Address Inputs
These inputs set the device address when address-
ing multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in
order to initiate communication with the CAT5251.
R
H
, R
L
: Resistor End Points
The four sets of R
H
and R
L
pins are equivalent to the
terminal connections on a mechanical potentiometer.
R
W
:
The four R
W
pins are equivalent to the wiper terminal
of a mechanical potentiometer.
Wiper
CS
:
CS
is the Chip select pin.
CS
low enables the
CAT5251 and
CS
high disables the CAT5251.
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5251
draws ZERO current in the Standby mode. A high to
low transition on
CS
is required prior to any sequence
Chip Select
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