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參數(shù)資料
| 型號(hào)： | CAT64LC20ZJI-TE7 |
| 英文描述： | 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| 中文描述： | SPI串行EEPROM |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 140K |
| 代理商： | CAT64LC20ZJI-TE7 |
7
CAT64LC10/20/40
Doc. No. 1021, Rev. A
a 16-bit data field is also required following the 8-bit
address field.
The CAT64LC10/20/40 requires an active LOW
CS
in
order to be selected. Each instruction must be preceded
by a HIGH-to-LOW transition of
CS
before the input of
the 4-bit start sequence. Prior to the 4-bit start sequence
(1010), the device will ignore inputs of all other logical
sequence.
Figure 4. Write Instruction Timing
Figure 5. Ready/
BUSY
Status Instruction Timing
Read
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one t
PD
after
the falling edge of the 16th clock (the last bit of the
address field). The READ operation is not affected by
the RESET input.
Write
After receiving a WRITE op code, address and data, the
device goes into the AUTO-Clear cycle and then the
* Please check instruction set table for address
SK
DI
CS
DO
RESET
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
RDY/
BUSY
SK
DI
CS
DO
RESET
WRITE INSTRUCTION
NEXT INSTRUCTION
HIGH
LOW
RDY/
BUSY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT64LC20ZJ-TE13 | 256K (32K x 8) Static RAM |
| CAT64LC20ZJ-TE7 | 256K (32K x 8) Static RAM |
| CAT64LC20ZP | 36-Mbit QDR™-II SRAM 2-Word Burst Architecture |
| CAT64LC40UATE13 | 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture |
| CAT64LC40UITE13 | 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT64LC20ZJ-TE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC20ZJ-TE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC20ZP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC20ZPI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT64LC20ZS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
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