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參數(shù)資料
| 型號： | CAT64LC40UTE13 |
| 英文描述： | 72-Mbit QDR™-II SRAM 2-Word Burst Architecture |
| 中文描述： | EEPROM的 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | CAT64LC40UTE13 |
5
CAT64LC10/20/40
Doc. No. 1021, Rev. A
INSTRUCTION SET
Instruction
Opcode
Address
Data
Read
64LC10
10101000
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10101000
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10101000
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write
64LC10
10100100
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10100100
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10100100
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write Enable
10100011
X X X X X X X X
Write Disable
10100000
X X X X X X X X
[Write All Locations]
(1)
10100001
X X X X X X X X
D15–D0
Figure 1. A.C. Testing Input/Output Waveform
(2)(3(4)
(C
L
= 100 pF)
Note:
(1)
(2)
(3)
(4)
(Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
Input Rise and Fall Times (10% to 90%) < 10 ns.
Input Pulse Levels = V
CC
x 0.2 and V
CC
x 0.8.
Input and Output Timing Reference = V
CC
x 0.3 and V
CC
x 0.7.
INPUT PULSE LEVELS
REFERENCE POINTS
VCC x 0.7
VCC x 0.3
VCC x 0.8
VCC x 0.2
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CAT64LC40V | 功能描述:電可擦除可編程只讀存儲器 (256x16) 4K RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT64LC40VA-GT3 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:4 kb SPI Serial EEPROM |
| CAT64LC40VA-T3 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:4 kb SPI Serial EEPROM |
| CAT64LC40VATE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1K/2K/4K-Bit SPI Serial E2PROM |
| CAT64LC40VGI | 制造商:Catalyst Semiconductor 功能描述: |
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