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參數(shù)資料
| 型號： | CAT64LC40ZSI |
| 英文描述： | 72-Mbit QDR™-II SRAM 2-Word Burst Architecture |
| 中文描述： | SPI串行EEPROM |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | CAT64LC40ZSI |
7
CAT64LC10/20/40
Doc. No. 1021, Rev. A
a 16-bit data field is also required following the 8-bit
address field.
The CAT64LC10/20/40 requires an active LOW
CS
in
order to be selected. Each instruction must be preceded
by a HIGH-to-LOW transition of
CS
before the input of
the 4-bit start sequence. Prior to the 4-bit start sequence
(1010), the device will ignore inputs of all other logical
sequence.
Figure 4. Write Instruction Timing
Figure 5. Ready/
BUSY
Status Instruction Timing
Read
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one t
PD
after
the falling edge of the 16th clock (the last bit of the
address field). The READ operation is not affected by
the RESET input.
Write
After receiving a WRITE op code, address and data, the
device goes into the AUTO-Clear cycle and then the
* Please check instruction set table for address
SK
DI
CS
DO
RESET
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
RDY/
BUSY
SK
DI
CS
DO
RESET
WRITE INSTRUCTION
NEXT INSTRUCTION
HIGH
LOW
RDY/
BUSY
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT64LC40ZSI-TE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
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| CAT64LC40ZS-TE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
| CAT6500HVA-T2 | 功能描述:電源開關(guān) IC - 配電 Pwr SELECTOR SWITCH RoHS:否 制造商:Exar 輸出端數(shù)量:1 開啟電阻（最大值）:85 mOhms 開啟時間（最大值）:400 us 關(guān)閉時間（最大值）:20 us 工作電源電壓:3.2 V to 6.5 V 電源電流（最大值）: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23-5 |
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