參數(shù)資料
型號: CAT93C56VP2I-T2
英文描述: 2-Kb Microwire Serial CMOS EEPROM
中文描述: 2 KB的Microwire串行EEPROM中的CMOS
文件頁數(shù): 8/18頁
文件大?。?/td> 370K
代理商: CAT93C56VP2I-T2
CAT93C56, CAT93C57
Doc. No. MD-1088 Rev. P
8
Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Write
After receiving a WRITE command (Figure 4), address
and the data, the CS (Chip Select) pin must be
deselected for a minimum of t
CSMIN
. The falling edge of
CS will start the self clocking clear and data store cycle
of the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C56/57 can be determined by
selecting the device and polling the DO pin. Since this
device features Auto-Clear before write, it is NOT
necessary to erase a memory location before it is
written into.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a
minimum of t
CSMIN
(Figure 5). The falling edge of CS will
start the self clocking clear cycle of the selected
memory location. The clocking of the SaK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C56/57 can
be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Figure 4. Write Instruction Timing
Figure 5. Erase Instruction Timing
SK
CS
DI
DO
tCSMIN
STANDBY
HIGH-Z
HIGH-Z
1
0
1
AN
AN-1
A0
DN
D0
BUSY
READY
STATUS
VERIFY
tSV
tHZ
tEW
SK
CS
DI
DO
STANDBY
HIGH-Z
HIGH-Z
1
AN
AN-1
BUSY
READY
STATUS VERIFY
tSV
tHZ
tEW
tCS
1
1
A0
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