參數(shù)資料
型號: CAT9555HV6I-G
廠商: ON Semiconductor
文件頁數(shù): 16/16頁
文件大小: 0K
描述: IC I/O EXPANDER 16BI 2C 24TQFN
標準包裝: 92
接口: I²C,串行,SMBus
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應商設備封裝: 24-TQFN(4x4)
包裝: 管件
包括: POR
CAT9555
http://onsemi.com
9
Registers and Bus Transactions
The CAT9555 internal registers and their address and
function are shown in Table 7.
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine which
register will be written or read.
The input port register is a read only port. It reflects the
incoming logic levels of the I/O pins, regardless of whether
the pin is defined as an input or an output by the configuration
register. Writes to the input port register are ignored.
Table 7. REGISTER COMMAND BYTE
Command (hex)
Register
0h
Input Port 0
1h
Input Port 1
2h
Output Port 0
3h
Output Port 1
4h
Polarity Inversion Port 0
5h
Polarity Inversion Port 1
6h
Configuration Port 0
7h
Configuration Port 1
Table 8. REGISTERS 0 AND 1 – INPUT PORT REGISTERS
bit
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
default
X
bit
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
default
X
Table 9. REGISTERS 2 AND 3 – OUTPUT PORT REGISTERS
bit
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
default
1
bit
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
default
1
Table 10. REGISTERS 4 AND 5 – POLARITY INVERSION REGISTERS
bit
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
default
0
bit
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
default
0
Table 11. REGISTERS 6 AND 7 – CONFIGURATION REGISTERS
bit
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
default
1
bit
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
default
1
Figure 9. Acknowledge Timing
18
9
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
ACK DELAY
ACK SETUP
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
(≥ tSU:DAT)
(≤ tAA)
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