參數(shù)資料
型號: CBTD16212DL
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 24-bit level shifting bus exchange switch WITH 12-BIT OUTPUT ENABIES
中文描述: CBT/FST/QS/5C/B SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56
封裝: PLASTIC, SSOP-56
文件頁數(shù): 5/10頁
文件大小: 90K
代理商: CBTD16212DL
Philips Semiconductors
Product data
CBTD16212
24-bit level shifting bus exchange switch
with 12-bit output enables
2001 Sep 28
5
AC CHARACTERISTICS
GND = 0 V; t
R;
C
L
= 50 pF
V
CC
= 5.0 V
0.5 V
= 5 0 V
±
0 5 V
SYMBOL
PARAMETER
FROM (INPUT)
TO
UNIT
(OUTPUT)
Min
Max
t
pd
Propagation delay
1
A or B
B or A
0 25
0.25
ns
t
en
Output enable time
to High and Low level
S
A or B
2
11.5
ns
t
dis
Output disable time
from High and Low level
S
A or B
1.5
8.5
ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V
INPUT
1.5 V
OUTPUT
t
PLH
t
PHL
SA00028
1.5 V
1.5 V
1.5 V
3 V
0 V
V
OH
V
OL
Waveform 1. Input (An) to Output (Yn) Propagation Delays
Output Control
(Low-level
enabling )
1.5 V
t
PZH
t
PHZ
V
OH
V
OL
t
PZL
t
PLZ
3.5 V
0 V
V
OL
+ 0.3 V
V
OH
– 0.3 V
SA00029
1.5 V
1.5 V
1.5 V
0 V
3 V
Output
Waveform 1
S1 at 7 V
(see Note)
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
Output
Waveform 2
S1 at Open
(see Note)
Waveform 2. 3-State Output Enable and Disable Times
TEST CIRCUIT AND WAVEFORMS
C
L
= 50 pF
500
Load Circuit
DEFINITIONS
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
TEST
S1
t
pd
open
t
PLZ
/t
PZL
7 V
t
PHZ
/t
PZH
open
SA00012
500
From Output
Under Test
S1
7 V
Open
GND
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