參數(shù)資料
型號(hào): CBTV4020EE
廠商: NXP Semiconductors N.V.
元件分類(lèi): 開(kāi)關(guān)
英文描述: 20-bit DDR SDRAM 2 : 1 MUX
封裝: CBTV4020EE/G<SOT761-1 (TFBGA72)|<<http://www.nxp.com/packages/SOT761-1.html<1<Always Pb-free,;
文件頁(yè)數(shù): 14/16頁(yè)
文件大小: 98K
代理商: CBTV4020EE
CBTV4020_3
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 4 April 2008
7 of 16
NXP Semiconductors
CBTV4020
20-bit DDR SDRAM 2 : 1 MUX
10. Static characteristics
[1]
All typical values are at VDD = 2.5 V, Tamb =25 °C.
[2]
When SEL is HIGH, DBn must be open and DAn can be HIGH or LOW. When SEL is LOW, DAn must be open and DBn can be HIGH or
LOW.
[3]
SEL = GND for testing DAn, and SEL = VDD for testing DBn.
[4]
Capacitance values are measured at 10 MHz and a bias voltage 3 V. Capacitance is not production tested.
[5]
Measured by the current between the host and the DIMM terminals at the indicated voltages on each side of the switch.
11. Dynamic characteristics
[1]
The propagation delay is based on the RC time constant of the typical ON-state resistance of the switch and a load capacitance, when
driven by an ideal voltage source (zero output impedance); 20
× 7 pF. Load capacitance = 7 pF. This parameter is not production
tested.
[2]
Skew is not production tested.
Table 7.
Static characteristics
Tamb =0 °C to +85 °C.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VIK
input clamping current
VDD = 2.3 V; II = 18 mA
-
1.2
V
ILI
input leakage current
VDD = 2.5 V; VI =VDD or GND;
SEL = GND or VDD
SEL
-
±100
A
host port
±100
A
SEL = GND for IIL (test)
DIMM port
±100
A
IDD
supply current
VDD = 2.5 V; IO = 0 mA; VI =VDD or GND
-
55
150
A
IOL
LOW-level output current
on DBn or DAn; VOL =1V
9.5
-
mA
Cin
control pin capacitance
VI = 2.5 V or 0 V
-pF
Con
switch on capacitance
VI = 1.5 V
[4] --10
pF
RON
ON resistance
VDD = 2.5 V; VA = 0.8 V; VB = 1.0 V
20
30
VDD = 2.5 V; VA = 1.7 V; VB = 1.5 V
20
30
Rpd
pull-down resistance
output; DAn (SEL = GND) or
DBn (SEL = VDD) = 0.5VDD
105
-
Table 8.
Dynamic characteristics
VDD = 2.5 V ± 0.2 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPD
propagation delay
from input DHn or DAn/DBn
to output DAn/DBn or DHn
140
-
ps
ten
enable time
from input SEL to output DAn/DBn or DHn
1
-
2
ns
tdis
disable time
from input SEL to output DAn/DBn or DHn
1
-
3
ns
tsk(o)
output skew time
any output to any output; Figure 7
2550ps
tsk(edge)
edge skew time
difference of rising edge propagation delay
and falling edge propagation delay;
2550ps
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