參數(shù)資料
型號(hào): CBTW28DD14ET
廠商: NXP SEMICONDUCTORS
元件分類: 編、解碼器及復(fù)用、解復(fù)用
英文描述: 14-bit bus switch-multiplexer for DDR2-DDR3 applications
中文描述: MULTIPLEXER, PBGA48
封裝: 4.50 X 4.50 MM, 0.80 MM PITCH, 0.50 MM PITCH, GREEN, PLASTIC, SOT1155-1, TFBGA-48
文件頁數(shù): 8/12頁
文件大?。?/td> 267K
代理商: CBTW28DD14ET
CBTW28DD14
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 1 — 20 July 2010
5 of 12
NXP Semiconductors
CBTW28DD14
14-bit bus switch/multiplexer for DDR2-DDR3 applications
10. Static characteristics
[1]
Typical values are at VDD = 1.8 V, Tamb =25 °C, and maximum loading.
11. Dynamic characteristics
Table 6.
Static characteristics
VDD = 1.4 V to 2.0 V; Tamb = 10 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Max
Unit
IDD
supply current
EN = HIGH; VDD =1.8 V
-
0.3
1
mA
EN = LOW; VDD = 1.8 V
--10
μA
IIH
HIGH-level input current
VDD =2.0 V; VI =VDD
--
±5
μA
IIL
LOW-level input current
VDD =2.0 V; VI =GND
-
±5
μA
VIH
HIGH-level input voltage
SEL, EN pins
0.8VDD
--
V
VIL
LOW-level input voltage
SEL, EN pins
-0.5
-
0.2VDD
V
VIK
input clamping voltage
VDD =2.0 V; II = 18 mA
-
0.7
1.2
V
Table 7.
Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tstartup
start-up time
supply voltage valid or EN going HIGH to
channel specified operating characteristics
--1
ms
trcfg
reconfiguration time
SEL state change to channel specified
operating characteristics
--1
ms
VI
input voltage
0.3
-
VDD +0.3
V
Vbias(DC)
bias voltage (DC)
0
-
2.0
V
α
il
insertion loss
channel is on; 0 Hz
≤ f ≤ 1.0 GHz
2.5
1.5
-
dB
channel is on; f = 2.5 GHz
4.5
-
dB
channel is off; 0 Hz
≤ f ≤ 3.0 GHz
-
20
dB
RLin
input return loss
channel is on; 0 Hz
≤ f ≤ 1.0 GHz
-
10
dB
α
ct
crosstalk attenuation
adjacent channels are on;
0Hz
≤ f ≤ 1.0 GHz
--
25
dB
B
bandwidth
3.0 dB intercept
-
2.5
-
GHz
tPD
propagation delay
from A port to B port or C port or vice versa
-
80
-
ps
tsk
skew time
from any output to any output
-
20
ps
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