參數(shù)資料
型號(hào)： CCU3001-I
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類： 微控制器/微處理器
英文描述： Central Control Unit
中文描述： MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 68/77頁(yè)
文件大小： 837K
代理商： CCU3001-I
CCU 3001, CCU 3001-I
MICRONAS INTERMETALL
68
Table 2–1:
I
2
C and IM bus interface registers
Address
Function
generate I
2
C start condition,
transfer Data as I
2
C address,
and set ACK=1
2D0H(w)
2D1H(w)
same as above, ACK=0
2D2H(w)
output 8 I
2
C Data bits,
set ACK=1
2D3H(w)
same as above, set ACK=0
output 8 I
2
C Data bits,
set ACK=1,
generate I
2
C stop condition
2D4H(w)
2D5H(w)
same as above,
set ACK=0
receive FIFO
2D6H(r)
2D7H(r)
status flags:
bit 0
not used
bit 1
1= receive
FIFO empty
1= contr-data-
FIFO half full
1= Bus busy
I
2
C data ACK
I
2
C adr ACK
bit 2
bit 3
bit 4
bit 5
bit 6
“OR”ed ACK
bit 7
not used
2D8H(w)
generate IM-address field
2D9H(w)
generate 8 IM-data bits
2DAH(w)
generate 8 IM-data bits and
the IM-stop condition
terminal select & speed
2DBH(w)
For example, the software has to work off the following
sequence (ACK =1) to read a 16-bit word from an I
2
C de-
vice address 10H (on condition that the bus is not ac-
tive):
–write 21H to
–write 0FFH to
–write 0FFH to
–read dev. address2D6H
–read 1. databyte 2D6H
–read 2. databyte 2D6H
2D0H
2D2H
2D4H
The value 21H in the first step results from the device ad-
dress in the 7 MSBs and the R/W-bit (read=1) in the LSB.
If the telegrams are longer, the software has to ensure
that neither the Control-Data-FIFO nor the Read-FIFO
can overflow.
To write data to this device:
–write 20H to
–write 1. databyte to
–write 2. databyte to
2D0H
2D2H
2D4H
The bus activity starts immediately after the first write to
the Control-Data-FIFO. In the I
2
C mode the transmis-
sion can be synchronized by an artificial extension of the
Low phase of the clock line. Transmission is not contin-
ued until the state of the clock line is High once again.
Thus a slave (software slaves!) can adjust the transmis-
sion rate to its own abilities.
The I
2
C/IM bus nterface s a pure Master system, Multi-
master busses are not realizable.
The ident, clock and data terminal pins have open-drain
outputs with weak pull-up transistors.
CCU 3000, CCU 3000-I
CCU 3000-I, CCU 3001-I
check
receive
FIFO empty flag
(bit 1, 2D7H) be-
fore read
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