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參數(shù)資料
| 型號： | CD-700-KAF-GFB-XX.XXX |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Complete VCXO Based Phase Lock Loop |
| 中文描述： | 基于完整的石英振蕩器鎖相環(huán) |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 147K |
| 代理商： | CD-700-KAF-GFB-XX.XXX |
CD-700, VCXO Based PLL
Performance Characteristics
Table 1. Electrical Performance
Parameter
Output Frequency (
ordering option
)
OUT1, 5.0 V option
OUT1, 3.3 V option
Supply Voltage
1
+5.0
+3.3
Supply Current
Output Logic Levels
Output Logic High
2
Output Logic Low
2
Output Transition Times
Rise Time
2
Fall Time
2
Input Logic Levels
Output Logic High
2
Output Logic Low
2
Loss of Signal Indication
Output Logic High
2
Output Logic Low
2
Nominal Frequency on Loss of Signal
Output 1
Output 2
Symmetry or Duty Cycle
3
Out 1
Out 2
RCLK
Absolute Pull Range (
ordering option
)
over operating temperature, aging, and
power supply variations
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Tel:1-88-VECTRON-1 Website: www.vectron.com
Page 2 of 14
Rev : 06Jul05
Symbol
Min
Typical
Maximum
77.760
77.760
5.5
3.63
63
0.5
5
5
0.5
0.5
±
75
±
75
40/60
45/55
40/60
Units
MHz
MHz
V
V
mA
V
V
ns
ns
V
V
V
V
ppm
ppm
%
%
%
ppm
1.000
1.000
V
DD
4.5
2.97
2.5
5.0
3.3
I
DD
V
OH
V
OL
t
R
t
F
V
IH
V
IL
V
OH
V
OL
2.0
2.5
SYM1
SYM2
RCLK
APR
±
50
±
80
±
100
0.5
0.3
Test Conditions for APR (+5.0 V option)
Test Conditions for APR (+3.3 V option)
Gain Transfer
Phase Detector Gain
+5V option
+3.3V option
Operating temperature (
ordering option
)
Control Voltage Leakage Current
1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded).
2. Figure 2 defines these parameters. Figure 3 illustrates the equivalent five gate TTL load and operating conditions under which
these parameters are tested and specified. Loads greater than 15 pF will adversely effect rise/fall time as well as symmetry.
3. Symmetry is defined as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation.
V
C
V
C
4.5
3.0
V
V
Positive
0.53
0.35
rad/V
rad/V
°
C
uA
0/70 or –40/85
I
VCXO
±
1
Figure 2. Output Waveform
Figure 3. OUT1, OUT2, RCLK, RDATA
Test Conditions (25
±
5°C)
80
%
1.4V
20
%
t
F
t
R
Period
On Time
+
-
+
-
I
C
V
C
13
7
.
1
μ
F
.01
μ
F
15pF
14
16
I
DD
650
V
DD
1.8k
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD-700-KAF-GFC-77.760 | 制造商:VECTRON 制造商全稱:Vectron International, Inc 功能描述:Complete VCXO Based Phase Lock Loop |
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| CD-700-KAF-GGB-12.000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Phase-Locked Loop |
| CD-700-KAF-GGB-12.288 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Phase-Locked Loop |
| CD-700-KAF-GGB-12.352 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Phase-Locked Loop |
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