參數(shù)資料
型號: CD4012BD
廠商: TEXAS INSTRUMENTS INC
元件分類: 門電路
英文描述: 4000/14000/40000 SERIES, DUAL 4-INPUT NAND GATE, CDIP14
封裝: CERAMIC, DIP-14
文件頁數(shù): 6/8頁
文件大?。?/td> 318K
代理商: CD4012BD
Product Folder: CD4011B, CMOS Quad 2-Input NAND Gate
Keyword
Part Number
PRODUCT SUPPORT: TRAINING
CD4011B, CMOS Quad 2-Input NAND Gate
DEVICE STATUS: ACTIVE
PARAMETER NAME CD4011B
Voltage Nodes (V) 5, 10, 15
Vcc range (V)
3 to 18
No. of Gates
4
FEATURES
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Propagation delay time = 60ns (typ.) at CL = 50 pF, VDD = 10 V
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Buffered inputs and outputs
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Standardized symmetrical output characteristics
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Maximum input current of 1 uA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C
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100% tested for quiescent current at 20 V
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5-V, 10-V, and 15-V parametric ratings
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Noise margin (over full package temperature range:
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 at VDD = 15 V
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Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"
Quad 2 Input—CD4011B
Dual 4 Input—CD4012B
Triple 3 Input—CD4023B
DESCRIPTION
CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are
buffered.
The CD4011B, CD4012B, and CD4023B types are supplied in 14-leasd hermetic dual-in-line ceramic packages (D and F suffixes), 14-lead dual-in-line plastic packages (E suffix), 14-lead dual-in-line small-
outline plastic package (M suffix), thin shrink small-outline package (PWR suffix), 14-lead small-outline package (NSR suffix), and in chip form (H suffix).
TECHNICAL DOCUMENTS
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DATASHEET
Full datasheet in Acrobat PDF: cd4011b.pdf (202 KB,Rev.B) (Updated: 05/03/2002)
APPLICATION NOTES
View Application Notes for Digital Logic
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file:///E|/042120003_HTML/cd4011b.html (1 of 3) [25-Apr-03 9:40:25 AM]
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相關代理商/技術參數(shù)
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