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參數(shù)資料
| 型號： | CD4027CJ |
| 英文描述： | J-K-Type Flip-Flop |
| 中文描述： | JK -型觸發(fā)器 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 99K |
| 代理商： | CD4027CJ |
5
www.fairchildsemi.com
C
AC Electrical Characteristics
(Note 4)
CD4020BC, CD4040BC T
A
=
25
°
C, C
L
=
50 pF, R
L
=
200k, t
r
=
t
f
=
20 ns, unless otherwise noted
Symbol
Parameter
t
PHL1
, t
PLH1
Propagation Delay Time to Q
1
Note 4:
AC Parameters are guaranteed by DC correlated testing.
Conditions
Min
Typ
250
Max
550
Units
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5V
V
DD
=
10V
V
DD
=
15V
Any Input
ns
100
75
150
210
150
330
t
PHL
, t
PLH
Interstage Propagation Delay Time
ns
from Q
n
to Q
n
+
1
60
45
100
125
90
200
t
THL
, t
TLH
Transition Time
ns
50
40
125
100
80
335
t
WL
, t
WH
Minimum Clock Pulse Width
ns
50
40
125
100
t
rCL
, t
fCL
Maximum Clock Rise and Fall Time
No Limit
ns
No Limit
No Limit
f
CL
Maximum Clock Frequency
1.5
4
MHz
4
5
10
12
200
t
PHL(R)
Reset Propagation Delay
450
ns
100
80
200
210
170
450
t
WH(R)
Minimum Reset Pulse Width
ns
100
80
5
210
170
7.5
C
IN
C
PD
Average Input Capacitance
pF
Power Dissipation Capacitance
50
pF
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CD4028 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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| CD4028AF | 制造商:Harris Corporation 功能描述: |
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