(Inputs: Logic 0 = GND, Logic 1 = VLS, CL
參數(shù)資料
型號: CDB4364
廠商: Cirrus Logic Inc
文件頁數(shù): 6/50頁
文件大小: 0K
描述: EVALUATION BOARD FOR CS4364
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 6
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
DAC 型: 電壓
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: CS4364
相關(guān)產(chǎn)品: CS4364-CQZR-ND - IC DAC 103DB 24BIT 6CH 48-LQFP
598-1059-ND - IC DAC 103DB 24BIT 6CH 48-LQFP
14
DS619F1
CS4364
SWITCHING CHARACTERISTICS - PCM
(Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF)
Notes:
14. After powering up, RST should be held low until after the power supplies and clocks are settled.
15. See Tables 1 - 3 for suggested MCLK frequencies.
Parameters
Symbol
Min
Max
Units
RST pin Low Pulse Width
1-
ms
MCLK Frequency
1.024
55.2
MHz
MCLK Duty Cycle
45
55
%
Input Sample Rate - LRCK (Manual selection)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
4
50
100
54
108
216
kHz
Input Sample Rate - LRCK (Auto detect)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
4
84
170
54
108
216
kHz
LRCK Duty Cycle
45
55
%
SCLK Duty Cycle
45
55
%
SCLK High Time
tsckh
8-
ns
SCLK Low Time
tsckl
8-
ns
LRCK Edge to SCLK Rising Edge
tlcks
5-
ns
SCLK Rising Edge to LRCK Falling Edge
tlckd
5-
ns
SDIN Setup Time Before SCLK Rising Edge
tds
3-
ns
SDIN Hold Time After SCLK Rising Edge
tdh
5-
ns
SDINx
t
ds
SCLK
LRCK
MSB
t
dh
t
sckh
t
sckl
t
lcks
MSB-1
Figure 1. Serial Audio Interface Timing
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