參數(shù)資料
型號： CDC922DLR
英文描述： CPU System Clock Generator
中文描述： CPU系統(tǒng)時鐘發(fā)生器
文件頁數(shù)： 9/17頁
文件大?。?/td> 292K
代理商： CDC922DLR
CDC922
133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS634 –JULY 28, 1999
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PCIx, 3V66x (Type 5)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
VDD = min to max,
IOH = –1 mA
VDD –
0.1 V
V
VDD = 3.135 V,
VDD = min to max,
VDD = 3.135 V,
VDD = 3.135 V,
VDD = 3.3 V,
VDD = 3.465 V,
VDD = 3.135 V,
VDD = 3.3 V,
VDD = 3.465 V,
VDD = 3.3 V,
VO = 0.5 VDD,
VO = 0.5 VDD,
IOH = –18 mA
IOL = 1 mA
IOL = 12 mA
VO = 1 V
VO = 1.65 V
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
VO = VDD or GND
VO/IOH
VO/IOL
2.4
VOL
Low level output voltage
Low-level output voltage
0.1
V
0.15
0.4
–33
–53
IOH
High-level output current
–53
mA
–16
–33
30
67
IOL
Low-level output current
70
mA
27
49
CO
Output capacitance
4.5
7.5
pF
ZO
Output impedance
High state
Low state
12
12
31
24
55
55
All typical values are measured at their respective nominal VDD values.
switching characteristics, V
DD
= 3.135 V to 3.465 V, T
A
= 0
°
C to 85
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Overshoot/undershoot
GND – 0.7 V
VDD + 0.7 V
VIH + 0.1 V
3
V
Ring back
VIL – 0.1 V
V
Stabilization time, PWR_DWN to PCIx
f(CPU) = 133 MHz
f(CPU) = 133 MHz
f(CPU) = 133 MHz
f(CPU) = 133 MHz
After SEL1, SEL0
0.05
ms
tdis3
Disable time, PWR_DWN to PCIx
50
ns
Stabilization time, PWR_DWN to CPUx
0.03
3
ms
tdis4
Disable time, PWR_DWN to CPUx
50
ns
Stabilization time
3
ms
After power up
3
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for
phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification.
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