參數(shù)資料
型號: CDC930
英文描述: 133-MHz Differential Clk Synthesizer/Drvr for PC Motherboards W/ 3-State Output
中文描述: 133 - MHz的差分時鐘合成器/適用于PC主板糯Drvr /三態(tài)輸出
文件頁數(shù): 11/17頁
文件大?。?/td> 240K
代理商: CDC930
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics, V
DD
= 3.135 V to 3.465 V, T
A
= 0
°
C to 85
°
C (continued)
3V48 (Type 3), C
L
= 20 pF, R
L
= 500
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc
3V48 clock period
f(3V48)= 48 MHz
f(3V48) = 48 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
f(3V48) = 48 MHz
f(3V48) = 48 MHz,
f(HCLK) = 100 or 133 MHz,
VDD = 3.3 V, Measured at 1.5 V
f(3V48) = 48 MHz,
Measured points at 1.5 V,
Measured at rising edges
15.03
ns
tjit(cc)
Cycle to cycle jitter
350
ps
tdc
Duty cycle
45%
55%
tsk(o)
3V48 output skew
3V48x
3V48x
250
ps
t(off)
3V48 clock to PCI
3V48x
PCIx
1.5
3.5
ns
tr
tf
Rise time
VO = 0.4 V to 2.4 V
VO = 0.4 V to 2.4 V
1
4
ns
Fall time
1
4
ns
The average over any 1–
μ
s period of time is greater than the minimum specified period.
REF (Type 3), C
L
= 20 pF, R
L
= 500
PARAMETER
REF clock period
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tc
tjit(cc)
tdc
tr
tf
The average over any 1–
μ
s period of time is greater than the minimum specified period.
f(REF)= 14.318 MHz
f(HCLK) = 100 or 133 MHz
f(REF) = 14.318 MHz
VO = 0.4 V to 2.4 V
VO = 0.4 V to 2.4 V
69.84
ns
Cycle to cycle jitter
1
ps
Duty cycle
52%
62%
Rise time
1
4
ns
Fall time
1
4
ns
相關PDF資料
PDF描述
CDC930DL CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC
CDD1933 TRANSISTOR | BJT | DARLINGTON | NPN | 80V V(BR)CEO | 4A I(C) | SOT-32
CDD2061D TRANSISTOR | BJT | NPN | 60V V(BR)CEO | 3A I(C) | TO-220AB
CDD2061E TRANSISTOR | BJT | NPN | 60V V(BR)CEO | 3A I(C) | TO-220AB
CDD2061F TRANSISTOR | BJT | NPN | 60V V(BR)CEO | 3A I(C) | TO-220AB
相關代理商/技術(shù)參數(shù)
參數(shù)描述
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