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參數(shù)資料
| 型號： | CDCLVP2104RHDR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER 2:8 2GHZ 28-VQFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 2 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | LVCMOS，LVDS，LVPECL，LVTTL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 2GHz |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-VQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
3,0mm(min)
0,75mm(typ)
0,33mm(typ)
SCAS889A
– OCTOBER 2009 – REVISED AUGUST 2011
APPLICATION INFORMATION
Thermal Management
Power consumption of the CDCLVP2104 can be high enough to require attention to thermal management. For
reliability and performance reasons, the die temperature should be limited to a maximum of +125
°C. That is, as
an estimate, ambient temperature (TA) plus device power consumption times θJA should not exceed +125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be
soldered down to ensure adequate heat conduction out of the package. Figure 12 shows a recommended land
and via pattern.
Figure 12. Recommended PCB Layout
Power-Supply Filtering
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is very critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,
they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It
is recommended to add as many high-frequency (for example, 0.1-
μF) bypass capacitors as there are supply
pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply
and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
very low dc resistance because it is imperative to provide adequate isolation between the board supply and the
chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required
for proper operation.
Copyright
2009–2011, Texas Instruments Incorporated
11
Product Folder Link(s): CDCLVP2104
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| CDCLVP2104RHDT | 功能描述:時鐘緩沖器 Low Jtr Dual 1:4 Uni-to-LVPECL Bfr RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CDCLVP2106 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12 LVPECL Output, High-Performance Clock Buffer |
| CDCLVP2106EVM | 功能描述:時鐘和定時器開發(fā)工具 CDCLVP2106 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| CDCLVP2106RHAR | 功能描述:時鐘緩沖器 Low Jitter Dual 1:6 Univ-to-LVPECL Bfr RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CDCLVP2106RHAT | 功能描述:時鐘緩沖器 Low Jitter Dual 1:6 Univ-to-LVPECL Bfr RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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