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參數(shù)資料
| 型號(hào)： | CH5101A-L |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Monochrome Digital Video Camera |
| 中文描述： | 單色的CMOS數(shù)碼攝像機(jī) |
| 文件頁(yè)數(shù)： | 23/32頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | CH5101A-L |
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CHRONTEL
CH5101A
201-0000-033 Rev 1.0, 6/2/99
23
Gamma
Programmable Sample and Hold Gain Register
Symbol: PSHG
Address:17h
Bits:8
Register PSHG specifies the gain of the programmable sample and hold before A/D conversion. There are eight gain
settings from a gain of 1.5x to a gain of 5.0x. When the autoshutter algorithm is controlling the gain value and this
register is read out, the autoshutter generated gain value is read instead of the actual IIC register content. Bits 5 and
4 (GAM[1:0]) control the gamma correction used, according to
Table 10
. Gamma is not available in ADDO mode
Clamp Level Register
Symbol:BCLMP
Address:18h
Bits:5
Register BCLMP specifies the offset level used in the black level clamp block. A value of 0 in register BCLMP will
nominally cause the A/D to output a value of zero for a dark cell input. The register value is 2’s complement and
ranges from -128 at maximum brightness to +127 at minimum brigtness. This register has no effect when the ASBE
bit is HIGH (default).
Miscellaneous Register
Symbol:MISC
Address:19h
Bits:7
Bits 0 and 1 of the MISC register control the border color that is output on each line containing active video for eight
13.5MHz clocks before the start of active video and eight 13.5MHz clocks after active video. This is only done
when the IC is placed into display mode four or five (M[2:0] = 4, 5). In these modes, the luminance data has been
interpolated to a pixel rate of 13.5MHz. Therefore, 8 pixels equals 592.5nS.
Table 11
describes the border colors.
BIT:
SYMBOL:
7
6
5
4
3
2
1
0
Reserved
Reserved
GAM1
GAM0
Reserved
PSHG2
PSHG1
PSHG0
TYPE:
DEFAULT:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
1
0
0
1
Table 10. Gamma Correction
GAM1
GAM0
0
0
1.0
0
1
1.6
1
0
2.2
1
1
2.2
BIT:
SYMBOL:
7
6
5
4
3
2
1
0
BCLMP7
BCLMP6
BCLMP5
BCLMP4
BCLMP3
BCLMP2
BCLMP1
BCLMP0
TYPE:
DEFAULT:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
0
0
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
Reserved
Reserved
DVDD
PD
VSP
HSP
BDR1
BDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT:
1
0
0
PUD4*
0
0
0
0
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