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參數(shù)資料
| 型號： | CH7006C-T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; Body Material:Aluminum; Series:PT06; Number of Contacts:18; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Circular Contact Gender:Socket; Insert Arrangement:14-18 |
| 中文描述： | 數(shù)字電視編碼器電腦功能 |
| 文件頁數(shù)： | 9/49頁 |
| 文件大?。?/td> | 338K |
| 代理商： | CH7006C-T |
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201-0000-026 Rev 2.1, 8/2/99
9
CHRONTEL
CH7006C
Multiplexed Mode
Each rising edge (or each rising and falling edge) of the XCLK signal will latch data from the graphics chip. The
multiplexed input data formats are shown in
Figure 5
and
6
. The Pixel Data bus represents an 8, 12, or 16-bit
multiplexed data stream, which contains either RGB or YCrCb formatted data. In IDF settings of 2, 4, 5, 7, 8 and 9,
the input data rate is 2X PCLK, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel,
encoded as shown in the tables below. When IDF = 6, the input data rate is 3X PCLK, and each triplet of Pn values
(e.g., P0a, P0b and P0c) will contain a complete pixel, encoded as shown in the tables below. When the input is
YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence
being set as Cb, Y, Cr, Y where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples — and the
following Y1 byte refers to the next luminance sample, per CCIR656 standards. However, the clock frequency is
dependent upon the current mode, (not 27MHz, as specified in CCIR656).
Figure 5: Multiplexed Pixel Data Transfer Mode
Table 4. RGB 8-bit Multiplexed Mode
IDF#
Format
Pixel#
Bus Data
7
RGB 5-6-5
P0b
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[5]
G0[4]
G0[3]
8
RGB 5-5-5
P0b
x
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[4]
G0[3]
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[5]
G1[4]
G1[3]
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
x
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[4]
G1[3]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
t
HSW
HS
t
HD
t
PH2
t
P2
t
HP2
t
SP2
D[15:0]
P0a
P0b
P1a
P1b
P2a
P2b
XCLK
DEC = 0
XCLK
DEC = 1
t
SP2
t
SP2
t
HP2
t
HP2
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