參數(shù)資料
型號(hào)： CH7006C-V
廠商： Electronic Theatre Controls, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; Body Material:Aluminum; Series:PT06; No. of Contacts:18; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Circular Contact Gender:Socket; Insert Arrangement:14-18
中文描述： 數(shù)字電視編碼器電腦功能
文件頁數(shù)： 11/49頁
文件大?。?/td> 338K
代理商： CH7006C-V
201-0000-026 Rev 2.1, 8/2/99
11
CHRONTEL
CH7006C
When IDF = 9 (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the
embedded sync will follow the CCIR656 convention, and the first byte of the “video timing reference code” will be
assumed to occur when a Cb sample would occur if the video stream was continuous. This is delineated in
Table 8
shown below.
.
Table 8. YCrCb Multiplexed Mode with Embedded Syncs
In this mode the S[7.0} contains the following data:
S[6]
=
F
=
S[5]
=
V
=
S[4]
=
H
=
1 during field 2, 0 during field 1
1 during field blanking, 0 elsewhere
1 during EAV (the synchronization reference at the end of active video)
0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3-0] are ignored.
Figure 6: Multiplexed Pixel Data Transfer Mode (IDF = 6)
IDF#
Format
Pixel#
Bus Data
9
YCrCb 8-bit
P1b
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
S[0]
P0a
FF
FF
FF
FF
FF
FF
FF
FF
P0b
00
00
00
00
00
00
00
00
P1a
00
00
00
00
00
00
00
00
P2a
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
P2b
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
P3a
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
P3b
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Table 9. RGB 8-bit Multiplexed Mode (24-bit Color)
IDF#
Format
6
RGB 8-bit
Pixel#
Bus Data
P0a
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P0b
G0[7]
G0[6]
G0[5]
G0[4]
G0[3]
G0[2]
G0[1]
G0[0]
P0c
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
P1a
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
G1[7]
G1[6]
G1[5]
G1[4]
G1[3]
G1[2]
G1[1]
G1[0]
P1c
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
P2a
B2[7]
B2[6]
B2[5]
B2[4]
B2[3]
B2[2]
B2[1]
B2[0]
P2b
G2[7]
G2[6]
G2[5]
G2[4]
G2[3]
G2[2]
G2[1]
G2[0]
P2c
R2(7)
R2(6)
R2(5)
R2(4)
R2(3)
R2(2)
R2(1)
R2(0)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
t
HSW
Pixel
D[7:0]
POut/
XCLK
HSYNC
t
HD
P0a
P0b
P0c
P1a
P1b
P1c
t
PH3
t
P3
t
HP3
t
SP3
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