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參數(shù)資料
| 型號： | CIP3250A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | Component Interface Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 26/44頁 |
| 文件大?。?/td> | 326K |
| 代理商： | CIP3250A |
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ADVANCE INFORMATION
CIP 3250A
26
Micronas
Table 2–10:
I
2
C-Bus operation, continued
Sub-
Address
(decimal)
Label
Bit No.
(LSB = 0)
Typical
Operation
Value
Function
I
2
C registers for SYNCHRONIZATION
17
NEGCLK
5
0
select active clockedge for inputs and outputs
0 = all inputs and outputs relate to rising edge at CLK input (DIGIT 3000)
1 = all inputs and outputs relate to falling edge at CLK input (DIGIT 2000)
17
SYNCSIM
0
1
HSYNC, VSYNC input
0 = FSY-/SKEW-protocol (see <17>D2KSYNC)
1 = HSYNC at FSY-pin, VSYNC at AVI-pin
(see also <07>FSYINV, <10>AVIINV)
17
D2KSYNC
1
0
sync protocol at FSY-pin
0 = DIGIT 3000 (FSY protocol)
AVI-Pin and FSY-Pin with trigger level at 1.2 Volt
1 = DIGIT 2000 (SKEW protocol)
AVI-Pin and FSY-Pin with Schmitt-Trigger characteristic
10
AVIINV
6
0
polarity of AVI signal
0 = vertical sync at falling edge of AVI (if <17>SYNCSIM = 1
1 = vertical sync at rising edge of AVI (if <17>SYNCSIM = 1)
07
FSYINV
7
0
polarity of FSY signal (see also <17>SYNCSIM)
0 = horizontal sync at falling edge of FSY (if <17>SYNCSIM = 1)
select always <07>FSYINV = 0 if <17>SYNCSIM = 0
1 = horizontal sync at rising edge of FSY (if <17>SYNCSIM = 1)
17
SYNCIN
7
0
UV (chroma) multiplex control of digital YUVin
0 = by AVI (active video in)
1 = by 72 bit data (DIGIT 2000)
17
SYNCOUT
6
0
UV (chroma) multiplex control of YUV output
0 = by AVO (active video out)
1 = by 72 bit data (DIGIT 2000)
17
P72BEN
2
0
72 bit data and clock bypass enable
0 = off
1 = on (DIGIT 2000)
Fig. 2–13:
H-sync reference generation
FSY
H-sync
AVO
(delay/clocks see table)
H-sync delay in respect to falling edge of FSY/
SKEW (H-sync is derived from FSY/SKEW)
D2KSYNC
<17>
1
X
delay
(clocks)
15
4
SYNCSIM
<17>
0
1
0
23
0
<23>AVHSTRT + 11
–
<22>AVPR clocks
Fig. 2–14:
DL2-setup
(<17>PXSKWON = 1)
AVI
DL2-RD
H-sync
(see Fig. 2
–
13)
DL2-WR
<21>DL2*2 + 2 clocks
4 clocks
82 clocks
24 clocks
102 clocks
<10>DL1ON = 0
<10>DL1ON = 1
48..212 clocks
Fig. 2–15:
DL2-reset during line 7
(<17>PXSKWON = 0)
DL2-reset
DL2-WR
DL2-RD
program delay
see <21>DL2
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