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參數(shù)資料
| 型號： | CK49X-495314 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 18/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALKIT 32BIT 600M 128PIN QFPDSP |
| 其它有關(guān)文件： | On-Chip IRC Prod Bullitin |
| 應(yīng)用說明： | Audio DSP Eval Kit Appl Note |
| 設(shè)計資源： | CS4953x4/4970X4 Designer Guide |
| 標準包裝： | 1 |
| 類型： | DSP |
| 適用于相關(guān)產(chǎn)品： | CS495314 |
| 所含物品： | 2 個板，線纜，電源 |
| 其它名稱： | 598-1938 |
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2
8
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The 12-channel (6-line) DAI port supports a wide variety of data input formats. The port is capable of accepting
PCM or IEC61937. Up to 32-bit word lengths are supported.
The port has two independent slave-only clock domains. Each data input can be independently assigned to a
clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which
off-loads the task of monitoring the S/PDIF receiver from the host. A time-stamping feature allows the input
data to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
Note:
There are two DAO ports. Each port can output eight channels of up to 32-bit PCM data. The port supports
data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave
mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two
ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can
be configured as a 192 kHz S/PDIF transmitter (data with embedded clock on a single line).
Note: Only one S/PDIF transmitter pin is available in the 128-pin package.
4.2.3 Serial Control Port 1 & 2 (I2C or SPI)
There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI
modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external
clock up to 50 MHz in SPI mode. It is present in both the 144- and 128-pin packages. This high clock speed
enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for
booting from external serial Flash memory or for audio sub-system control. SCP2 does not include the
SCP2_BSY# pin in the 128-pin package.
4.2.4 Parallel Control Port
The CS4953xx parallel port supports both Motorola and Intel interfaces. It can be used for both control and
data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin
package.
4.2.5 External Memory Interface
The external memory interface controller supports up to 128 Mb of SDRAM, using a 16-bit data bus.
4.2.6 General Purpose Input/Output (GPIO)
Many of the CS4953xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output,
an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge,
active-low, or active-high.
4.2.7 Phase-Locked Loop (PLL)-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the
DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on
the DAO port for driving audio converters. The CS4953xx defaults to running from the external reference
frequency and can be switched to use the PLL output after overlays have been loaded and configured, either
through master boot from an external serial FLASH or through host control. A built-in crystal oscillator circuit
with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or
2:1.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS4953xx pins are multi-functional. For details on pin functionality, refer to the CS4953xx
Hardware User’s Manual.
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