參數(shù)資料
型號(hào)： CL81188AQC208-3
英文描述： Gate Array
中文描述： 門陣列
文件頁(yè)數(shù)： 9/12頁(yè)
文件大?。?/td> 118K
代理商： CL81188AQC208-3
CL81188A Laser-Configured ASIC
Page 9
AC Electrical Specifications
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
IOD
IOE register data delay
0.7
0.8
0.9
ns
t
IOC
IOE register control signal delay
1.7
1.8
1.9
ns
t
IOE
Output enable delay
1.7
1.8
1.9
ns
t
IOCO
IOE register clock to output delay
1.0
1.0
1.0
ns
t
IOCOMB
IOE combinatorial delay
0.3
0.2
0.1
ns
t
IOSU
IOE register setup time before clock
1.4
1.6
1.8
ns
t
IOH
IOE register hold time after clock
0.0
0.0
0.0
ns
t
IOCLR
IOE register clear delay
1.2
1.2
1.2
ns
t
IN
Input pad and buffer delay
1.5
1.6
1.7
ns
t
ZX
Output buffer disable delay
C
L
= 5 pF
1.4
1.6
1.8
ns
Speed: -2
Speed: -3
Speed: -4
t
OD1
Output buffer and pad delay
Slow Slew Rate = off,
V
CCIO
= 5.0v, C
L
= 35 pF
1.1
1.4
1.7
ns
t
OD2
Output buffer and pad delay
Slow Slew Rate = off,
V
CCIO
= 5.0v, C
L
= 35 pF
1.6
1.9
2.2
ns
t
OD3
Output buffer and pad delay
Slow Slew Rate = off,
V
CCIO
= 5.0v, C
L
= 35 pF
4.6
4.9
5.2
ns
t
ZX1
Output buffer disable delay
Slow Slew Rate = off,
V
CCIO
= 5.0v, C
L
= 35 pF
1.4
1.6
1.8
ns
t
ZX2
Output buffer disable delay
Slow Slew Rate = off,
V
CCIO
= 5.0v, C
L
= 35 pF
1.6
2.1
2.3
ns
t
ZX3
Output buffer disable delay
Slow Slew Rate = off,
V
CCIO
= 5.0v, C
L
= 35 pF
4.9
5.1
5.3
ns
8K tbl 06C
I/O Element Timing Parameters
[5]
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
DRR
Register to register delay via four LEs,
three row interconnects, and
four local interconnects
16
20
25
ns
t
ODH
Output data hold time after clock
1.0
1.0
1.0
ns
Speed: -2
Speed: -3
Speed -4
8K tbl 07B
External Timing Parameters
[4]
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