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參數(shù)資料
| 型號： | CL81188AQC240-2 |
| 英文描述： | Gate Array |
| 中文描述： | 門陣列 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 118K |
| 代理商： | CL81188AQC240-2 |
CL81188A Laser-Configured ASIC
Page 10
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max Unit
t
LUT
Look up table delay for data-in
2.0
2.5
3.2
ns
t
CLUT
Look up table delay for carry-in
0.0
0.0
0.0
ns
t
RLUT
Look up table delay for LE register feedback
0.9
1.1
1.5
ns
t
GATE
Cascade gate delay
0.0
0.0
0.0
ns
t
CASC
Cascade chain routing delay
0.6
0.7
0.9
ns
t
CICO
Carry-in to carry-out delay
0.4
0.5
0.6
ns
t
CGEN
Data-in to carry-out delay
0.4
0.5
0.7
ns
t
CGENR
LE register feedback to carry-out delay
0.9
1.1
1.5
ns
t
C
LE register control signal delay
1.6
2.0
2.5
ns
t
CH
Clock high time
1.7
1.7
2.7
ns
t
CL
Clock low time
1.7
1.7
2.7
ns
t
CO
LE register clock-to-output delay
0.4
0.5
0.6
ns
t
COMB
Combinatorial delay
0.4
0.5
0.6
ns
t
SU
LE register setup time before clock
0.8
1.1
1.2
ns
t
H
LE register hold time after clock
0.9
1.1
1.5
ns
t
PRE
LE register preset delay
0.6
0.7
0.8
ns
t
CLR
LE register clear delay
0.6
0.7
0.8
ns
8K tbl 08A
Speed: -2
Speed: -3
Speed: -4
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
LABCASC
Cascade delay between LEs in different LABs
0.3
0.4
0.4
ns
t
LABCARRY
Carry delay between LEs in different LABs
0.3
0.4
0.4
ns
t
LOCAL
LAB local interconnect delay
0.5
0.5
0.7
ns
t
ROW
Row interconnect routing delay
5.0
5.0
5.0
ns
t
COL
Column interconnect routing delay
3.0
3.0
3.0
ns
t
DIN_C
Dedicated input to LE control delay
5.0
5.0
5.5
ns
t
DIN_D
Dedicated input to LE data delay
7.0
7.0
7.5
ns
t
DIN_IO
Dedicated input to IOE control delay
5.0
5.0
5.5
ns
Speed: -2
Speed: -3
Speed: -4
8K tbl 09B
AC Electrical Specifications cont.
Logic Element Timing Parameters
[5]
Interconnect Timing Parameters
[5]
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