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參數(shù)資料
| 型號(hào)： | CLC014AJE/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 2/21頁 |
| 文件大小： | 0K |
| 描述： | IC CABLE EQUALIZER ADAPTV 14SOIC |
| 標(biāo)準(zhǔn)包裝： | 55 |
| 應(yīng)用： | 醫(yī)用型 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 配用： | SD901EVK-ND - BOARD EVAL CLC014, 016, 011, 006 SD014EVK-ND - BOARD EVALUATION CLC014 |
| 其它名稱： | *CLC014AJE *CLC014AJE/NOPB CLC014AJE |
OBSOLETE
SNLS010E – JUNE 1998 – REVISED APRIL 2013
BLOCK DESCRIPTION
The CLC014 is an adaptive equalizer that reconstructs serial digital data received from transmission lines such
as coaxial cable or twisted pair. Its transfer function approximates the reciprocal of the cable loss characteristic.
The block diagram in Figure 18 depicts the main signal conditioning blocks for equalizing digital data at the
receiving end of a cable. The CLC014 receives baseband differential or single-ended digital signals at its inputs
DI and DI.
The Equalizer block is a two-stage adaptive filter. This filter is capable of equalizing cable lengths from zero
meters to lengths that require 40 dB of boost at 200 MHz.
The Quantized Feedback Comparator block receives the differential signals from the equalizer filter block. This
block includes two comparators. The first comparator incorporates a self-biasing DC restore circuit. This is
followed by a second high-speed comparator with output mute capability. The second comparator receives and
slices the DC-restored data. Its outputs DO and DO are taken from the collectors of the output transistors. MUTE
latches DO and DO when a TTL logic low level is applied.
The Adaptive Servo Control block produces the signal for controlling the filter block, and outputs a voltage
proportional to cable length. It receives differential signals from the output of the filter block and from the
quantized-feedback comparator (QFBC) to develop the control signal. The servo loop response is controlled by
an external capacitor placed across the AEC+ and AEC
pins. Its output voltage, as measured differentially
across AEC+ and AEC
, is roughly proportional to the length of the transmission line. For Belden 8281 coaxial
cable this differential voltage is about 1.5 mV/meter. Once this voltage exceeds 500 mV, no additional
equalization is provided.
The Carrier Detect (CD) block monitors the signal power out of the equalizing filter and compares it to an
internal reference to determine if a valid signal is present. A CMOS high output indicates that data is present.
The output of CD can be connected to the MUTE input to automatically latch the outputs (DO and DO),
preventing random transitions when no data is present.
The Output Eye Monitor (OEM) provides a single-ended buffered output for observing the equalized eye
pattern. The OEM output is a low impedance high-speed voltage driver capable of driving an AC-coupled 100
load.
Figure 18. CLC014 Block Diagram
10
Copyright 1998–2013, Texas Instruments Incorporated
Product Folder Links: CLC014
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參數(shù)描述 |
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| CLC014AJE-TR13/NOPB | 功能描述:IC CABLE EQUALIZER ADAPT 14-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| CLC016 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Data Retiming PLL with Automatic Rate Selection |
| CLC016_02 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Data Retiming PLL with Automatic Rate Selection |
| CLC016ACQ | 制造商:Texas Instruments 功能描述:Data Retiming PLL w/Auto Rate,CLC016ACQ |
| CLC016ACQ/NOPB | 功能描述:IC DATA RETIMING PLL 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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