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參數(shù)資料
| 型號： | CM17699 |
| 廠商： | 意法半導體 |
| 英文描述： | COLOR PDP DRIVER MODULE |
| 中文描述： | 彩色PDP驅動模塊 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 250K |
| 代理商： | CM17699 |
6.4 - Block Diagram
6 - STV7699 SPECIFICATIONS
(continued)
B4
A4
B3
A3
B2
A2
16-BIT SHIFT REGISTER
P3
P63
F/R
16-BIT SHIFT REGISTER
P1
P61
2
79
V
Pins 6-15-24-35
40-46-57-66-75
V
CC
B1
A1
STB
BLK
POL
OUT1
OUT64
STV7699
CLK
V
Pins 1-29-30
51-52-80
LATCH
Q1
Q64
Q2
Q63
P64
P1
P63
P4
16-BIT SHIFT REGISTER
P2
P62
16-BIT SHIFT REGISTER
P4
P64
V
Pins 41-81
V
Pins 90 to 93
HIZ
7
6.5 - Circuit Description
STV7699 contains all the logic and the power
circuits necessary to drive the colums of a Plasma
Display Panel (P.D.P.). Data are shifted at each low
to high transition of the (CLK) shift clock. Data are
input in a 4-bit wide data bus to A1 - A4 input (case
of forward shift mode ; F/R = low). After 16 shifts,
the first nibble is available at the serial outputs
B1 - B4. These outputs can be used to cascade
several drivers to perform any horizontal resolution.
CLK, Ai and Bi inputs are Smith trigger inputs to
improve the noise margin.
The Forward/Reverse (F/R) input is used to select
the direction of the shift register.
The maximum frequency of the shift clock is
20MHz.
All the output data are held and memorized into the
latch stage when the Latch input (STB) is high.
When it is at low level, data are transferred from
the shift register to the latch and to the output power
stage.
Output state can be forced to high impedance by
pulling low HIZ input.
When BLK is Low, all the outputs are forced to low
level or high level according to POL signal value.
Output state copy data that was input, with the
same polarity, when BLK, HIZ and POL are High.
V
SSLOG
, V
SSSUB
and V
SSP
are not internally con-
nected.
V
SSLOG
and V
SSSUB
must be connected as close as
possible to the logical reference ground of the
application.
Table 1 :
Power Output Truth Table
Data STB POL BLK HIZ
Driver
Output
HIZ
L
H
Qn (1)
L
H
Comments
x
x
x
x
L
H
x
x
x
H
L
L
x
L
H
H
H
H
x
x
L
H
H
H
L
H
H
H
H
H
High impedance
Forced to low
Forced to high
Latched data
Copy data
Copy data
Note 1 :
Qn is the value memorised in the latch stage ; it is the value
of the parallel shift register output stage after n Clock
pulses.
A data loaded in the shift register is read on the
output power stage without inversion of its polarity.
Table 2 :
Control Table
F/R
L
H
Ai
Bi
Comments
Input
Output
Output
Input
Forward shift
Reverse shift
CM17699
7/11
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