CM2006
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4
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1) Symbol
Parameter
Conditions
Min
Typ
Max
Units
ICC_DDC
VCC_DDC Supply Current
VCC_DDC = 5.0 V
10
mA
ICC
VCC Supply Current
VCC = 5 V; SYNC inputs at GND or VCC;
SYNC outputs unloaded
1
mA
VCC = 5 V; SYNC inputs at 3.0 V;
SYNC outputs unloaded
2.0
mA
VF
ESD Diode Forward Voltage
IF = 10 mA
1.0
V
VIH
Logic High Input Voltage
2.0
V
VIL
Logic Low Input Voltage
0.5
V
VHYS
Hysteresis Voltage
400
mV
VOH
Logic High Output Voltage
IOH = 0 mA, VCC = 5.0 V; (Note 2) 4.0
V
VOL
Logic Low Output Voltage
IOL = 0 mA, VCC = 5.0 V; (Note 2) 0.15
V
ROUT
SYNC Driver Output Resistance
VCC = 5.0 V; SYNC Inputs at GND or 3.0 V
7
15
24
W
IIN
Input Current
VIDEO Inputs
VCC = 5.0 V; VIN = VCC or GND
±10
mA
SYNC_IN1, SYNC_IN2 Inputs
VCC = 5.0 V; VIN = VCC or GND
±10
mA
IOFF
Level Shifting NMOSFET “OFF” State
Leakage Current
(VCC_DDC VDDC_IN) < 0.4 V;
VDDC_OUT = VCC_DDC
10
mA
(VCC_DDC VDDC_OUT) < 0.4 V;
VDDC_IN = VCC_DDC
10
mA
IBACKDRIVE Current conducted from input pins when
Vcc is powered down.
VCC < VINPUT_PIN; (Note 5) 10
mA
VON
Voltage Drop Across Levelshifting
NMOSFET when ”O(jiān)N”
VCC_DDC = 2.5 V; VS = GND; IDS = 3 mA
0.18
V
CIN_VID
VIDEO Input Capacitance
VCC = 5.0 V; VIN = 2.5 V; f = 1 MHz
3
pF
VCC = 2.5 V; VIN = 1.25 V; f = 1 MHz
3.5
pF
tPLH
SYNC Driver L => H Propagation Delay
CL = 50 pF; VCC = 5.0 V; Input tR and tF < 5 ns
12
ns
tPHL
SYNC Driver H => L Propagation Delay
CL = 50 pF; VCC = 5.0 V; Input tR and tF < 5 ns
12
ns
tR, tF
SYNC Driver Output Rise & Fall Times
CL = 50 pF; VCC = 5.0 V; Input tR and tF < 5 ns
3
ns
VESD1
ESD Withstand Voltage, Sync_out pins
only
VCC = 5 V; (Notes 3 and 4) ±2
kV
VESD
ESD Withstand Voltage
VCC = 5 V; (Notes 3 and 5) ±8
kV
1. All parameters specified over standard operating conditions unless otherwise noted.
2. These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER.
3. Per the IEC6100042 International ESD Standard, Level 4 contact discharge method. BYP and VCC must be bypassed to GND via a low
impedance ground plane with a 0.22 mF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the
applicable pins and GND. ESD pulses can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3,
SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. All pins are ESD protected to the industry standard ±2 kV Human Body Model
(MILSTD883, Method 3015).
4. This specification applies to the SYNC_OUT pins only.
5. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2.