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參數(shù)資料
| 型號： | CM2031-A0TR |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HDMI RX PORT P/I 38-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP （0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 38-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | CM2031-A0TROSDKR |
CM2031
http://onsemi.com
5
Figure 2. Dynamic DDC Pullups
(Discrete Top, CM2031 Bottom; 3.3 V ASIC Left, 5 V Cable Right)
I2C Low Level Shifting
In addition to the Dynamic Pullups described in the
previous section, then CM2031 also incorporates improved
I2C lowlevel shifting on the DDC_CLK_IN and
DDC_DAT_IN lines for enhanced compatibility.
Typical discrete NFET level shifters can advertise
specifications for low RDS[on], but usually state relatively
high V[GS] test parameters, requiring a ‘switch’ signal (gate
voltage) as high as 10 V or more. At a sink current of 4 mA
for the ASIC on DDC_XX_IN, the CM2031 guarantees no
more than 140 mV increase to DDC_XX_OUT, even with
a switching control of 2.5 V on LV_SUPPLY.
Additionally, when I2C devices are driving the external
cable, an internal pulldown on DDC_XX_IN guarantees
that the VOL seen by the ASIC on DDC_XX_IN is equal to
or lower than DDC_XX_OUT.
Multiport DDC Multiplexing
Additionally, by switching LV_SUPPLY, the DDC/HPD
blocks can be independently disabled by engaging their
inherent “backdrive” protection. This allows N:1
multiplexing of the lowspeed HDMI signals without any
additional FET switches.
CONSUMER ELECTRONICS CONTROL (CEC)
The Consumer Electronics Control (CEC) line is a high
level command and control protocol, based on a single wire
multidrop open drain communication bus running at
approximately 1 kHz (See Figure 3). While the HDMI link
provides only a single pointtopoint connection, up to ten
(10) CEC devices may reside on the bus, and they may be
daisy chained out through other physical connectors
including other HDMI ports or other dedicated CEC links.
The high level protocol of CEC can be implemented in
a simple microcontroller or other interface with any I/OD
(input/opendrain) GPIO.
RX
TX
I/OD
GPIO
CEC
Figure 3. Typical mC I/OD Driver
To limit possible EMI and ringing in this potentially
complex connection topology, the rise and falltime of this
line are limited by the specification. However, meeting the
slewrate limiting requirements with additional discrete
circuitry in this bidirectional block is not trivial without an
additional RX/TX control line to limit the output slewrate
without affecting the input sensing (See Figure 4).
Figure 4. ThreePin External Buffer Control
RX
TX
TX_EN
CEC
Slew Rate
Limited
3State Buffer
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