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參數(shù)資料
| 型號(hào)： | CM6504IP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 8-PIN SINGLE PFC CONTROLLER WITH 50% PWM CLOCK SIGNAL |
| 中文描述： | 8針單PFC控制器的50％PWM時(shí)鐘信號(hào) |
| 文件頁(yè)數(shù)： | 11/13頁(yè) |
| 文件大小： | 182K |
| 代理商： | CM6504IP |
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CM6503/4
8-PIN S
INGLE
PFC C
ONTROLLER
W
ITH 50%
PWM
C
LOCK
S
IGNAL
50% PWM Clock
PWMCLK is the PWM Clock signal for the down stream DC
to DC PWM stage. This signal will not be on until the PFC
boost output reaches steady state which means VFB has
reaches 2.45V. (Typical PFC boost output is around 380V.
Then PWMCLK will send out 50% clock signal which has
2002/07/16
Preliminary
Rev. 0.2
Champion Microelectronic Corporation
Page 11
been perfectly aligned with PFCOUT signal which is leading
edge modulation.
In CM6503, 50% PWM Clock is running at 67.5K hz. In
CM6504, 50% PWM Clock is running at 135Khz.
APPLICATION CIRCUIT (CM6503/4)
D8
R7
F1
AC IN
19.4V
R1A
UVLO
0.75V
10mS
.
.
.
D2
C15
400K ohm
-
C8
To synchronize
next DC to DC
stage
R1B
VREF OK
+
R5
D3
S
R
Q
Q
R
PFCCLKB
PWMCLK
OSC
.
.
67KHz
134KHz
VFB
2
GND
Q1
R2
CFilter
67KHz
67KHz
R1C
C7
18V
C14
VCC OVP
+
-
.
-
C1
SS
VREFOK
PFC ILIMIT
+
-
.
8
PWMCLK
C8
.
.
+
+
OUT
U1
SUM
.
.
.
50%
UVLO
.
.
+
-
.
T1
RAMP
+
-
.
PFC OVP
+
-
.
-
7
VCC
PFCCMP
+
-
.
-1V
Tri-Fault
4
VEAO
C5
D1
R3
CM6504
fpfc=
1K ohm
3
ISENSE
1V
D4
pwm clk=
Z1
100K ohm
1
PFCOUT
D5
2.5V
CM6503
fpfc=
pwm clk=
C4
VIN OK
+
-
.
+
6
IAC
D7
RFIlter
T1
2.5V
C9
FAULTB
gmv
2.5V
R11
D11
0.5V
VREF OK
ISENSEAMP
VCC
SS
PWM CLK
5
VFB
R4
2.75V
C13
VCC
RAC
PFCCLKB
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