參數(shù)資料
型號(hào)： COLDFIRE3UM
英文描述： Version 3 ColdFire Core User＇s Manual
中文描述： 版本3 ColdFire內(nèi)核的用戶手冊(cè)
文件頁(yè)數(shù)： 91/253頁(yè)
文件大小： 1762K
代理商： COLDFIRE3UM
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Master Bus Operation
3-32
ColdFire2/2M User’s Manual
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
3.8.1 Access Errors
The system hardware can use the
MTEAB
signal to abort the current bus cycle when a fault
is detected as shown in
Figure 3-18
. An access error is recognized during a bus cycle in
which MTEAB is asserted. When the ColdFire2/2M recognizes an access error condition,
the access is terminated immediately. A line access that has MTEAB asserted for one of the
four longword transfers aborts without completing the remaining transfers.
When
MTEAB
is asserted to terminate a bus cycle, the ColdFire2/2M can enter access error
exception processing immediately following the bus cycle, or it can defer processing the
exception in the following manner. The instruction prefetch mechanism requests instruction
words from the instruction memory unit before it is ready to execute them. If an access error
occurs on an instruction fetch, the ColdFire2/2M does not take the exception until it attempts
to use the instruction. Should an intervening instruction cause a branch or should a task
switch occur, the access error exception for the unused access does not occur. Similarly, if
an access error is detected on the second, third, or fourth longword transfer for a line read
access, an access error exception is taken only if the execution unit is specifically requesting
that longword. Otherwise, the line is not placed in the cache, and the ColdFire2/2M repeats
the line access when another access references the line. If a misaligned operand spans two
longwords in a line, an access error on either the first or second transfer for the line causes
exception processing to begin immediately. An access error termination for any write
accesses or for read accesses that reference data specifically requested by the execution
unit causes the ColdFire2/2M to begin exception processing immediately. Refer to
Section
4Exception Processing
for details of access error exception processing.
When an access error terminates an access, the contents of the corresponding cache can
be affected. For a cache line read to replace a valid instruction line, the cache line being filled
is invalidated before the bus cycle begins and remains invalid if the replacement line access
is terminated with an access error.
Note that if an access is made to a space that is masked, it simply becomes mapped to the
next valid space; no access error is generated. See Section 5.5, Interactions Between K-
Bus Memories, for further information. When a write error occurs on a buffered write, an
access error will be generated but will not be reported on the instruction that generated the
write.
Access errors only occur because of the following:
1)
MTEAB
asserts
2)
MMU error; i.e. trying to write in a write protected space
Table 3-9. MTAB and MTEAB Assertion Results
MTAB
Don’t Care
MTEAB
Asserted
RESULT
Access Error—Terminate and Take Access Error Exception
This exception cannot be masked
Normal Cycle Terminate and Continue
Insert Wait States
Asserted
Negated
Negated
Negated
F
Freescale Semiconductor, Inc.
n
.
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