參數(shù)資料
型號: COP8CBR9IMT8/NOPB
廠商: National Semiconductor
文件頁數(shù): 84/111頁
文件大?。?/td> 0K
描述: IC MCU EEPROM 8BIT 32K 48-TSSOP
標準包裝: 38
系列: COP8™ 8C
核心處理器: COP8
芯體尺寸: 8-位
速度: 20MHz
連通性: Microwire/Plus(SPI),UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 39
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
包裝: 管件
其它名稱: *COP8CBR9IMT8
*COP8CBR9IMT8/NOPB
COP8CBR9IMT8
COP8CBR9IMT8-ND
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Figure 5-23 shows the Interrupt block diagram.
Figure 5-23. Interrupt Block Diagram
5.15.2 MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated
enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state
of the interrupt enable bit, combined with the GIE bit determines whether an active pending flag actually
triggers an interrupt. All of the maskable interrupt pending and enable bits are contained in mapped
control registers, and thus can be controlled by the software.
A maskable interrupt condition triggers an interrupt under the following conditions:
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced,
a maskable interrupt must wait until that service routine is completed.)
An interrupt is triggered only when all of these conditions are met at the beginning of an instruction. If
different maskable interrupts meet these conditions simultaneously, the highest-priority interrupt will be
serviced first, and the other pending interrupts must wait.
74
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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