參數(shù)資料
型號(hào): CP80C88-2Z
廠商: Intersil
文件頁(yè)數(shù): 18/38頁(yè)
文件大小: 0K
描述: IC PWM CONTROLLER
標(biāo)準(zhǔn)包裝: 99
處理器類型: 80C88 8/16-位
速度: 8MHz
電壓: 4.75 V ~ 5.25 V
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-DIP
包裝: 管件
25
FN2949.4
February 22, 2008
FIGURE 13. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.
FIGURE 14. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
NOTE:
Setup requirements for asynchronous signals only to guarantee recognition at next CLK.
FIGURE 15. ASYNCHRONOUS SIGNAL RECOGNITION
NOTE:
Setup requirements for asynchronous signals only to
guarantee recognition at next CLK.
FIGURE 16. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
Waveforms (Continued)
CLK
TCLGH
RQ/GT
PREVIOUS GRANT
AD7-AD0
RD, LOCK
A19/S6-A16/S3
S2, S1, S0
TCLCL
ANY
CLK
CYCLE
> 0-CLK
CYCLES
PULSE 2
80C88
TGVCH (14)
TCHGX (15)
TCLGH (44)
PULSE 1
COPROCESSOR
RQ
TCLAZ (25)
80C88 GT
PULSE 3
COPROCESSOR
RELEASE
(SEE NOTE)
TCHSZ (26)
(1)
TCLGL
(43)
COPROCESSOR
TCHSV (21)
(44)
CLK
HOLD
HLDA
A15-A8
A19/S6-A16/S3
RD, WR, I/O/M, DT/R, DEN, SSO
80C88
THVCH (13)
TCLHAV (36)
≥ 1CL
1 OR 2
CYCLES
TCLAZ (19)
COPROCESSOR
80C88
TCLHAV (36)
CYCLE
TCHSZ (20)
THVCH (13)
TCHSV (21)
(SEE NOTE)
AD7-AD0
NMI
INTR
TEST
CLK
SIGNAL
TINVCH (SEE NOTE)
(13)
ANY CLK CYCLE
CLK
LOCK
TCLAV
ANY CLK CYCLE
(23)
TCLAV
(23)
80C88
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