參數(shù)資料
型號(hào)： CP80C88Z
廠商： Intersil
文件頁(yè)數(shù)： 3/38頁(yè)
文件大?。?/td> 0K
描述： IC PWM CONTROLLER
標(biāo)準(zhǔn)包裝： 99
處理器類型： 80C88 8/16-位
速度： 5MHz
電壓： 4.5 ~ 5.5V
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
11
FN2949.4
February 22, 2008
I/O Addressing
In the 80C88, I/O operations can address up to a maximum
of 64k I/O registers. The I/O address appears in the same
format as the memory address on bus lines A15-A0. The
address lines A19-A16 are zero in I/O operations. The
variable I/O instructions, which use register DX as a pointer,
have full address capability, while the direct I/O instructions
directly address one or two of the 256 I/O byte locations in
page 0 of the I/O address space. I/O ports are addressed in
the same manner as memory locations.
FIGURE 5. BASIC SYSTEM TIMING
(4 + NWAIT) = TCY
T1
T2
T3
T4
TWAIT
T1
T2
T3
T4
TWAIT
(4 + NWAIT) = TCY
GOES INACTIVE IN THE STATE
JUST PRIOR TO T4
A19-A16
S6-S3
A7-A0
D15-D0
VALID
A7-A0
DATA OUT (D7-D0)
READY
WAIT
MEMORY ACCESS TIME
ADDR
STATUS
CLK
ALE
S2-S0
ADDR DATA
RD, INTA
READY
DT/R
DEN
WP
S6-S3
A19-A16
A15-A8
ADDR
A15-A8
BUS RESERVED
FOR DATA IN
TABLE 2.
S2
S1
S0
CHARACTERISTICS
0
Interrupt Acknowledge
0
1
Read I/O
010
Write I/O
011
Halt
1
0
Instruction Fetch
1
0
1
Read Data from Memory
1
0
Write Data to Memory
11
1
Passive (No Bus Cycle)
TABLE 3.
S4
S3
CHARACTERISTICS
0
Alternate Data (Extra Segment)
01
Stack
1
0
Code or None
11
Data
80C88
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