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參數(shù)資料
| 型號： | CPC1465D |
| 廠商： | IXYS Integrated Circuits Division |
| 文件頁數(shù)： | 3/15頁 |
| 文件大小： | 0K |
| 描述： | IC DC TERMINATION 16-SOIC |
| 標準包裝： | 47 |
| 功能： | DC 信號終端 |
| 接口： | ISDN，SHDSL |
| 電路數(shù)： | 1 |
| 功率（瓦特）： | 1W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 包括： | 光耦合器 |
| 其它名稱： | CLA206 CPC1465D-ND |
INTEGRATED CIRCUITS DIVISION
R04
www.ixysic.com
11
CPC1465
The turn-off timing circuit deactivates the sealing
current hold circuit when 1 mA of sealing current has
been removed for 100 ms but ignores periods of loss
up to 3 ms.
2.5 Photo-Diode (PD) Output Behavior
Output from the PD pin provides a minimum of 0.2 mA
of photo-diode drive current for the opto-coupler LED
anytime sealing current exceeds 1 mA.
Because LED current is interrupted whenever loop
current is interrupted, the opto-coupler provides an
excellent means of indicating loop availability for
designs with a sealing current requirement.
2.6 On-State Behavior
2.6.1 Typical Conditions
On-state sealing current levels are determined by the
network’s power feed circuit and the loop’s dc
impedance. To compensate for low loop resistance or
very high loop voltage, the CPC1465 limits the
maximum sealing current to 70 mA.
The CPC1465 manages package power dissipation
by shunting excess sealing current through the 2.2 k
4W power resistor located between the PR+ and PR-
pins.
2.6.2 Over-Voltage Conditions
Potentials in excess of 100 V applied to the tip and
ring interface will cause the CPC1465 to disable the
sealing current hold circuit and enter a standby state
with very little current draw. Once the over-voltage
condition is removed, the CPC1465 automatically
resumes normal operation.
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