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參數(shù)資料
| 型號： | CPC5710NTR |
| 廠商： | IXYS Integrated Circuits Division |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 0K |
| 描述： | IC PHONE LINE MONITOR 8-SOIC |
| 產(chǎn)品目錄繪圖： | Phone Line Monitor 8-SOIC |
| 標準包裝： | 1 |
| 系列： | LITELINK® |
| 功能： | 電話線監(jiān)控器（PLM） |
| 電路數(shù)： | 1 |
| 電源電壓： | 3 V ~ 5.5 V |
| 電流 - 電源： | 10mA |
| 功率（瓦特）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 標準包裝 |
| 包括： | 全波振鈴檢測器 |
| 產(chǎn)品目錄頁面： | 2629 (CN2011-ZH PDF) |
| 其它名稱： | CLA301DKR |
INTEGRATED CIRCUITS DIVISION
CPC5710N
R03
www.ixysic.com
5
2. Using CPC5710N
2.1 LIN/CMP Input
The LIN/CMP input selects the active output, either
the detector output CMPOUT or the linear outputs,
LINOUT- and LINOUT+. Set LIN/CMP low for linear
output and high for comparator output. Note that both
outputs cannot be used at once.
With LIN/CMP at logic low (LIN/CMP = 0), the
amplifier outputs are biased at a nominal 1VDC and
CMPOUT is held high. With LIN/CMP at logic high
(LIN/CMP = 1), LINOUT+ is 0V and LINOUT- is 2V.
Figure 1. LIN/CMP Timing for Caller-ID Signal
Reception
2.2 Amplifier Design
Considerations
Amplifier inputs are biased at a nominal 1.25VDC, the
internal voltage reference. The internal common-mode
circuitry maintains the average of the inputs at
1.25VDC. For example, if one input reaches 1.3V, the
common-mode circuit drives the other input to 1.2V.
2.2.1 Linear Amplifier Gain
Display feature information (caller ID) and voice
signals are coupled through the linear amplifier. In
North America, CID data signals are typically sent
between the first and second ringing signal burst.
Referring to Figure 5., signal gain from tip and ring to
LINOUT+ and LINOUT- is determined by:
where
is the frequency of the signal.
Application Note AN-117 Customize Caller ID Gain and
Ringing Detect Voltage Threshold is a spreadsheet for
trying different component values in this type of circuit.
2.3 Detector Considerations
2.3.1 Ringing Signal Detection
The CPC5710N detector is a full-wave configuration.
Ringing signals will assert the output on both positive
and negative parts of the ringing waveform. Hysteresis
is employed by the internal comparator circuit to
provide noise immunity. The set-up of the detector
causes CMPOUT output pulses to remain low for most
of the ringing signal positive and negative half-cycles.
CMPOUT returns high when the ringing signal is near
the zero-voltage crossing.
Figure 2. CMPOUT Relative to Input
2.3.2 Setting Ringing Detection Threshold
The ringing detection threshold depends on the
component values of the input network. The values for
these components shown in the application circuit are
recommended for typical operation. Referring to
Figure 5., the ringing detection threshold can be
changed according to the following formula:
Caller ID data
LIN/CMP
Signal levels not to scale
2s
500 ms
3s
475 ms
2s
GAINCID dB
20
6RSNPD
4RSNP RSNPD
+
2
1
fC
SNP
2
--------------------------
+
-----------------------------------------------------------------------------------------
log
=
CMPOUT
Ringing Signal
VRINGPK
750mV
RRSNPD
-------------------
4RSNP RSNPD
+
2
1
f
RINGCSNP
2
--------------------------------------
+
=
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