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參數(shù)資料
| 型號： | CR16MBR5VJE8Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 105K |
| 代理商： | CR16MBR5VJE8Y |
6
C
3.14
CR16CAN
The CR16CAN device contains a FullCAN class, CAN serial
bus interface for applications that require a high speed (up to
1MBits per second) or a low speed interface with CAN bus
master capability. The data transfer between CAN and the
CPU is established by 15 memory mapped message buffers,
which can be individually configured as receive or transmit
buffers. An incoming message is filtered by two masks, one
for the first 14 message buffers and another one for the 15th
message buffer to provide a basic CAN path. A priority de-
coder allows any buffer to have the highest or lowest transmit
priority. Remote transmission requests can be processed au-
tomatically by automatic reconfiguration to a receiver after
transmission or by automated transmit scheduling upon re-
ception. In addition, a time stamp counter (16-bits wide) is
provided to support real time applications.
The CR16CAN device is a fast core bus peripheral, which al-
lows single cycle byte or word read/write access. A set of di-
agnostic features (such as loopback, listen only, and error
identification) support the development with the CR16CAN
module and provide a sophisticated error management tool.
The CR16CAN receiver can trigger a wake-up condition out
of the power-save modes via the Multi-Input Wake-Up mod-
ule.
3.15
ACCESS.BUS INTERFACE
The ACCESS.bus interface module (ACB) is a two-wire seri-
al interface with the ACCESS.bus physical layer. It is also
compatible with Intel’s System Management Bus (SMBus)
and Philips’ I
2
C bus. The ACB module can be configured as
a bus master or slave, and can maintain bi-directional com-
munications with both multiple master and slave devices.
The ACCESS.bus receiver can trigger a wake-up condition
out of the power-save modes via the Multi-Input Wake-Up
module.
3.16
A/D CONVERTER
The A/D Converter (ADC) module is a 12-channel multi-
plexed-input analog-to-digital converter. The A/D Converter
receives an analog voltage signal on an input pin and con-
verts the analog signal into an 8-bit digital value using suc-
cessive approximation. The CPU can then read the result
from a memory-mapped register. The module supports four
automated operating modes, providing single-channel or 4-
channel operation in single or continuous mode.
3.17
ANALOG COMPARATORS
The Dual Analog Comparator (ACMP2) module contains two
independent analog comparators with all necessary control
logic. Each comparator unit compares the analog input volt-
ages applied to two input pins and determines which voltage
is higher. The CPU uses a memory-mapped register to con-
trol the comparator and to obtain the comparison results. The
comparison result can also be applied to comparator output
pins.
3.18
DEVELOPMENT SUPPORT
A powerful cross-development tool set is available from Na-
tional Semiconductor and third parties to support the devel-
opment and debugging of application software for the
CR16MBR5. The tool set lets you program the application
software in C and is designed to take full advantage of the
CompactRISC architecture.
There are In-System Emulation (ISE) devices available for
the CR16MBR5 from iSYSTEM, as well as lower-cost eval-
uation boards. See your National Semiconductor sales rep-
resentative for current information on availability and
features of emulation equipment and evaluation boards.
4.0
Memory Map
The CompactRISC architecture supports a uniform linear ad-
dress space of 2 megabytes. The device implementation of
this architecture uses only the lowest 128K bytes of address
space, ranging from 0000 to 1FFFF hex. Table 1 is a memory
map showing the types of memory and peripherals that occu-
py this memory space. Address ranges not listed in the table
are reserved and should not be read or written.
Table 1
Device Memory Map
Address
Range (hex)
Description
0000-7FFF
ROM Program Memory
a
C000-CBFF
Static RAM (3K bytes)
E000-E5FF
ISP Memory(1.5K bytes)
E800-EFFF
Lower Endurance Flash EEPROM Data
Memory (2K bytes)
F000-F07F
High Endurance Flash EEPROM Data
Memory (128 bytes)
F400-F7FF
CAN buffers and registers (1K bytes)
F800-FAFF
BIU Peripherals (768 bytes)
FB00-FB06
Port B registers
FB00-FBFF
I/O Expansion + Ports PB & PC (256 bytes)
FB10-FB16
Port C registers
FC00-FFFF
Peripherals and other I/O Ports (1K bytes)
FC40-FC8A
Clock, Power Management, and Wake-Up
registers
FCA0-FCA8
Port G registers
FCC0-FCC8
Port H registers
FF00-FF08
Port L registers
FD20-FD28
Port F registers
FE00-FE1E
Interrupt Control Unit registers
FE40-FE4E
USART 1 registers
FE60-FE66
MICROWIRE registers
FE80-FE8E
USART 2 registers
FEC0-FECA
ACCESS.bus registers
FEE0-FEE8
Port I registers
FF20-FF2A
Timer and WATCHDOG registers
FF40-FF50
Multi-function Timer1 registers
FF60-FF70
Multi-function Timer2 registers
FF80-FFA4
Versatile Timer Unit registers
FFC0-FFD0
A/D Converter registers
FFE0-FFE0
Analog Comparator register
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